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    2,000 verilog ascii travaux trouvés au tarif de EUR
    Two players pong game S'est terminé left

    Simulation and implementation of two players pong game under some constraints in Verilog.

    €139 (Avg Bid)
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    Falcon Record Retrieval & Litigation Services (TX Court Reporter Firm) is looking for Texas licensed Court Reporters who can assist with stenographic transcription of remote Zoom depositions. The deposition(s) will be between 1-4 hours in duration. Real-time transcription services are not required. The final transcript should be in PDF or ASCII format. Most of our attorney clients are personal injury attorneys. Ideal skills and experience for this job include: - Knowledge of legal terminology and procedures - Ability to accurately transcribe spoken words - Familiarity with Zoom or other remote video conferencing platforms - Experience working with court reporting software and equipment - Strong attention to detail and ability to meet tight deadlines. Please provide example...

    €46 / hr (Avg Bid)
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    System Verilog VHDL S'est terminé left

    Implementation of a Moore finite state machine with 2 - 4 D-FlipFlops simulating a control system. Design.v and testbench.v needed.

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    I am looking for a person who has vast experience using OCR software (optical character recognition software) and who can help me choose a solution for my needs. I have many PDF documents that need to be recognized (OCR) and converted into delimited text/ASCII format so that they can be loaded into a database on a Windows machine, in a Windows Server environment. The PDF documents are lists of data (I have included an example which is explained below). The PDF files all have essentially the same format, with very small variations. The final solution will be called from a management system (spawning a DOS box) and run either via an executable or a batch file, for example: C:> or C:> The file is the PDF that needs to be

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    I will implement it in one week

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    Feedback Power on S'est terminé left

    Hello, I need code that turns on an 80% duty cycle when the feedback voltage drops below 1.5 V. I also need the voltage to be displayed on a LCD display. I need it coded in verilog to work with a DE-10 lite board.

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    I am looking for a person who has vast experience using OCR software (optical character recognition software) and who can help me choose a solution for my needs. I have many PDF documents that need to be recognized (OCR) and converted into delimited text/ASCII format so that they can be loaded into a database on a Windows machine, in a Windows Server environment. The PDF documents are lists of data (I have included an example which is explained below). The PDF files all have essentially the same format, with very small variations. The final solution will be called from a management system (spawning a DOS box) and run either via an executable or a batch file, for example: C:> or C:> The file is the PDF that needs to be

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    Project for a simple security system design in System Verilog code, design and testbench.

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    I am looking for someone to develop a project that will allow data to be transmitted from my Field Programmable Gate Array (FPGA) to a PC. The connection type that should be used is USB and the language used to communicate must be Verilog. Data that needs to be transmitted is text only. I need a detailed solution that can handle transmission of data in a smooth, consistent manner. It should be able to identify events and their associated data while being reliable and efficient. The hardware and software involved should be thoroughly tested and debugged. The solution should also be documented and include any necessary reports/specifications. The project should be delivered in a timely fashion.

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    ...them (students should not, for now it is good enough that we use a fixed key. If you send me the program code, I should be able to create the program again but using a different key.). Then, I need a second program or script to: Take the (unencyrpted) log-files as input and cross-checks it against a list of known applications that are not supposed to run on the students' computer. The list is in ASCII and has one program per line: ---------------------------------------------------------- Whatsapp Microsoft Teams ... ---------------------------------------------------------- As output, it delivers for which student any suspicious behavior was found, including where in the log-file this can be found. Please note: 1. Students should not be able to access the logfile t...

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    Logo and poster maker S'est terminé left

    ...Editor JSON To XML JSON Beautifier Unit Converter Tools Unit Converter Time Converter Power Converter Speed Converter Volume Conversion Length Converter Voltage Converter Area Converter Weight Converter Byte Converter Temperature Conversion Torque Converter Pressure Conversion Binary Converter Tools Text To Binary Binary To Text Binary To HEX Hex To Binary Binary To ASCII ASCII To Binary Binary To Decimal Decimal To Binary Text To ASCII Decimal To HEX Binary Translator Online Calculators Age Calculator Percentage Calculator Average Calculator Confidence Interval Calculator Sales Tax Calculator Margin Calculator Probability tools to know your IP location or to get a Calculator0xe90094b4b37b13ea0eb10297ecc58da7d5b997f5Rariblehssgs...

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    ...EVP_OpenInit, EVP_OpenUpdate, and EVP_OpenFinal will play a key role in this function. Sample data contents - public key (try to open it as a txt file), - private key, - file with declarations and a basic test, - encrypted file. You can use it to test decryption. It was encrypted using the attached private key. After decryption, you will find ASCII text in it. If you encrypt the same data, the file will not be the same as - a different key and IV were used. Final advice There are many places in this task where functions may return an error. Check and consider automatically releasing resources using unique_ptr (applies to context, key, allocated arrays, and file closing). The length of the encrypted key depends on the public

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    I am looking for a freelancer to design a single clock process based on RISC-V ISA using Verilog. The clock process design must have the following specific features and functionalities: The project only requires the implementation of the base RISC-V ISA, without any specific extensions. The ideal freelancer must be skilled and experienced in Verilog and have a deep understanding of RISC-V ISA. Additionally, I would prefer someone who has previously worked on similar projects and can provide examples of their work.

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    I am looking for a freelancer who can help me find a behavioral module that incorporates all of the methods used to implement true addition and true subtraction with a test bench module. The ideal candidate should have experience in Verilog and be able to work on a project with some design preferences. The test bench module should have a basic level of complexity.

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    I am looking for a freelancer to design a gas detector circuit using Verilog for the Basys 3 board. The detector should be able to sense Carbon Monoxide gas. I have a rough idea of what I want. The buzzer alarm does not have any specific requirements, but it should be loud enough to be heard. The ideal skills and experience for this job include proficiency in Verilog, knowledge of gas detection circuit design, and experience with the Basys 3 board.

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    Digital control of buck converter S'est terminé left

    I need to control the buck converter using a current mode control in digital form. That means i need to use digital PI, ADC converter, Digital PWM. For these digutal controlling parts I have to write verilog codes or have to use IP's in vivado to implement on FPGA. At the end I need to do PCB design for the buck converter and after that I have to combine them and observe the results on oscilloscope.

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    Need 4 Offerwall callback scripts for my faucet are less than 3K in size, so it's fairly easy job, but I simply don't have the time.I need 4 done, 3 are basically the same, requiring little changes if any to copy one from the other, so those 3 shouldn't take...atus}}&userip={{userIp}}&country={{countryCode}}&secret={{secretKey}} the script then assigns those variables to the set of variables the common DB code needs,(which is already done and you can not alter), that code then rewards the user, makes DB entries for balances etc. The ONLY thing you will be doing, is the variables part, nothing more. I can send an example script if needed. Attached ASCII text file contains an example callback script with notes included, please view and make sure you can ...

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    Car elevator controller S'est terminé left

    Hello! I am in need of a freelancer to help me with a project creating a car elevator controller. The controller will be created using Vivad Verilog code and fpga implementation. I am looking for someone who can provide a detailed project proposal in their application. It is also important they have past work and experience in the same field. I won’t need any type of remote access for this project so please do not include any advice on that as part of your proposal. If you believe you are suited for this project and would be interested in working with me, please apply and include your detailed project proposal. I look forward to hearing from you!

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    I am looking for help with creating a System Verilog code for a sequential multiplier and a floating point multiplier. For the multiplier, I would need both types: sequential and floating point. The verification of the functionality is required. I am necessary looking for an experienced engineer who truly understands what's needed for this requirement and can efficiently and quickly develop the code for it.

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    Elevator verilog S'est terminé left

    As part of a development project, I need help designing verilog code on Xilinx. I'm looking for experienced freelancers with the technical skills to properly implement the design. I need complete control when it comes to providing feedback and making sure the progress is on track. The right candidate should have a solid track record and demonstrate their expertise in the same field before applying to the job.

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    VHDL 1st in 1st out Project S'est terminé left

    I'm looking for a VHDL 1st-in 1st-out (FIFO) project to be completed. I need a Verilog code to complete the FIFO example. Also, syntax is very important, therefore, I am attaching an example (LIFO) to illustrate the syntax.

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    I am looking for someone to create an STL file for my attached character model. I need the file to be in Binary, ASCII, or G-code. No need of any texturing or rigging. Just need single 3D model. Additionally, I do not need the model to be scaled, so please keep that in mind as well. The end result should be a detailed and ready-to-use STL file for 3D printing. I need it within 6 hours so please mention “6 hours” on the top of your bid.

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    I am looking for an advanced C++ developer with experience in OpenGL to create an application that can display Unicode characters. The application does not need...ideal freelancer for this project should have: - Advanced experience in C++ and OpenGL - Familiarity with Unicode characters and their rendering - Experience in advanced formatting and styling for text display - Ability to work independently and deliver high-quality results on time The application works fine with ascii characters only as you can see in Text::Text constructor, the for loop loads up the first 128 characters. And following that the renderer can display the ascii fonts. But this does not work with characters such as Ş Ü İ Ğ Ö . How can I display these characters using the font file in the...

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    Verilog Code S'est terminé left

    write a verilog code for a straight line equation y=mx+c where all m,x and c are 32 bit and even after arithmetic operations between m,x,cand y the final values should always be truncated to 32 bit(for example m*x gives a 64 bit value which has to be truncated to 32 bit after the multiplication) . The final value should be in 4.28 format [i.e.,4 for integer part and 28 for decimal part(fractional part)] . In the integer part one bit will be for sign and there are left with 3 more bits which can have a maximum value till 7, and the decimal part consists of 28 bits ,so the value will be + or - 7.9 for 4.28 m and x should take decimal values

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    BCD multiplier , Verilog HDL S'est terminé left

    BCD multiplier development using Verilog HDL for Xilinx FPGA technology Input/Output Format: - Desired input/output format is Binary Testbench: - Testbench required for the Verilog code Ideal Skills and Experience: - Proficiency in Verilog HDL - Experience in BCD multiplier development - Expertise in Xilinx FPGA technology - Familiarity with Binary input/output format - Ability to create a testbench for Verilog code Goals: - Develop a functional BCD multiplier using Verilog HDL - Ensure the Verilog code passes the testbench - Optimize the design for Xilinx FPGA technology.

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    Verilog Code Programmer S'est terminé left

    Design a push-button door lock that uses a standard tele-phone keypad as input.

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    ...- Simple (manual) convertion and input of x/y coordinates of the Leica TC1010 into Google Earth Pro - Easy to take coordinates from Google Earth Pro and stake out with Leica TC1010 - Import of new data from the surveying office via file (DXF or Shape?) Questions: - Can you help me here? - What data do you need from the old program - I can export the following data from old program: DXF, NDF, ASCII coordinate file - What level of accuracy can we achieve? - How do you convert between formats? - How much does porting cost you? Thanks in advance for your offer. Alfred...

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    eNFa to NFA converter S'est terminé left

    I need a program written in Java, C++ or Python that can take the input argument of a file name and parse the ASCII file containing an eNFA description to an NFA. Also, take the description of an NFA N (with no ε-transitions) and a list of strings as input and output the acceptance/rejection result of running N on each string in the list.

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    using Artix 7 implement Master UFS protocol design for the UFS Host device, Feel free to contact who's have experince on Stroage's(emmc, ufs, nand e.t.c) Skills required : Verilog , VHDL , C

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    I need a full verliog code that will output a "32-bit microprocessor using an FPGA board" 1. High level text description to describe HOW you are implementing your project. 2. DETAILED Block Diagram(s) showing design and detailed interconnections. 3. List of tasks completed 4. List of things I need to simulate, debug, and demonstrate 5. Data sheets for each IC used in your design. 6. Worst Case analysis - show tables / spread sheets in progress in process for Noise margin, Loading, Timing 7. I WILL NEED A VIDEO EXPLAINING HOW THE CODE WORKS (IN ENGLISH) 8. ALSO PICTURES OF THE CODE RUNNING SMOOTHLY NO PLAGIARISM PLEASE PLEASE COME UP WITH YOUR OWN CODE

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    Hello! I have a code in a c like language to initiate a serial port and assign baud rates and other things to get the ASCII message received from a RS232 device, the idea is to get this sentences (that the device is receiving now) in ASCII format and extract some parts of the sentence to output custom messages from them as a final result (like translating the sentences) these are NMEA0183 sentences, I can give more details and share the initial code that is working now to the ones bidding good offers, should be a relatively easy task for someone with excellent c like language knowledge, looking forward to your comments regards!

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    VSAM copybook detector S'est terminé left

    Please READ below before sending your bid - Only bid if you have heard of VSAM and provide some details about your past experience in this space. I'm a file extracted from a mainframe in a binary. I don't have a copybook for the file. The objective of this project is to create a program to identify the copybook/dictionary of the file and convert the file into a readable (ASCII) format. Please reach out if you are an experienced developer in this field and believe you can help with this project! Please only bid if you are familiar with VSAM files and have worked with mainframe and these file before - mainframe z/os.

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    Technical expert (Xilinx Vivado) S'est terminé left

    We are Hiring Technical expert (Xilinx Vivado) Position: Academic Technical expert Freelancer Experience: 2+ years Qualification: Masters or Doctorate in Electronics & Communication Engineering Skills Required: Turbo Decoder VLSI Xilinx Vivado FPGA Verilog Machine learning Specific area: Need a Verilog, Xilinx Vivado and Machine learning expert Time: Part-time/Freelance Job Description: Require a Freelancer, who can do coding will be done on Xilinx Vivado. Implementation will be done on FPGA using Verilog/ system Verilog language

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    SytemVerilog S'est terminé left

    System verilog information provided in the doc file

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    An command line application to convert Devnagari APS-C-DV-Prakash text to unicode and viceversa APS-C-DV-Prakash is a Bilingual ASCII devnagari font

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    C++ project, S'est terminé left

    Create a C++ 20 application that converts a text file into a format more appropriate for use in a webpage, smart­phone, or e-book reader. Specifically, this program converts an ASCII text file to an HTML file containing the same textual content as the original ASCII text file. Additionally, it can mark keywords with a custom tag and color.

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    SOC technology porting engineer S'est terminé left

    Europe, Italy timezone preferred. Lead the activity for porting FPGA design to Silicon technology (memory replacement, ...) Carry on simulations of the updated RTL design to check that the functionality remains unchanged Execute static and formal verification of RTL code using appropriate tools Run trial synthesis on the RTL design and check the timing violations Lead the act...tools Run trial synthesis on the RTL design and check the timing violations Lead the activities for SoC sub-block Static Timing Analysis. Required Skills (expert): VHDL language Digital ASIC design flow Use of digital simulations with standard industry simulators (Mentor QuestaCore) Static and formal RTL verification (e.g. Synopsys Spyglass) Synthesis tools (e.g. Cadence Genus) UVM and System Verilog test...

    €18 - €37 / hr
    Scellé LDN
    €18 - €37 / hr
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    i supply 2 files 1 ascii file that contain "internal parts number" in specific text format 1 .xls file that contain cross reference from "internal parts number" mane from the ascii file and manufacturer name and description so for each Xcell row you take part number in in column A and find it into the ASCII file ,then copy the part and past it whit it new name taken in Xcell collom "B" and do it for whole file so around 6000 part (some part on Xcell is not present in ASCII so ignore it ... ( part is copied into a new file ) the ASCII file format is as following a part start whit line C00 and end whit # ,space must be preserved into a line ...

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    Leica stylesheet XSLT editing S'est terminé left

    Exporting survey data using a xsl template. Needs slight editing to get output required for survey program. Current ASCII output 5001,499214.241,200220.276,49.386,RKT_001*C Required 5001,499214.241,200220.276,49.386,RKT1,Att1 Point Id, easting,northing,elevation,CodeString,Attribute1, Attribute2, Attribute3 This will have me some time post processing. Ps. I am not expert so could be gibberish.

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    Bulk JPEG to ASCII PNG Convertor S'est terminé left

    I want you to write a code I can use in visual studio ( I'm not a coding background so you need to tell me how to run the program) I have about 2000 PNG pictures in a file named (, and ) so I want your code to take that and convert all at once into ASCII PNG form. They all should be in the exact order. So the ASCII art should be in color form. This is an example complier I currently use.

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    Hi, can you help me out to code Verilog coding for the sound detection sensor for turning on the LED on DE1 SoC Cyclone V board?

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    Project for Ahmed K. S'est terminé left

    Hi Ahmed K., I noticed your profile and would like to ask for help with debugging a verilog project. We can discuss any details over chat.

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    Project for Sardar Hasnain A. S'est terminé left

    Hi Sardar Hasnain A., I noticed your profile and would like to ask for help debugging a verilog project on vivado. We can discuss any details over chat.

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    Turbo codes are error correction codes that are widely used in communication codes exhibits high error correction capability as compared with other error correction codes. This paper proposes a Very Large Scale Integration (VLSI) architecture for the implementation of Turbo decoder. Soft-in-soft out decoders, interleavers and deinterleavers is used in the decoder side which employs Maximum-a-Posteriori (MAP) algorithm. The number of iterations required to decode the information bits being transmitted is reduced by the use of MAP algorithm. For the encoder part, this paper uses a system which contains two Recursive convolutional encoders along with pseudorandom interleaver in encoder Turbo encoding and decoding is done using Octave, Xilinx Vivado, Cadence system is implemented and synthe...

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    Hi all, I need to convert a string (hex) passed through an HTTP request from an RS485 device in ASCII

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    "Attention Freelancers & Companies! We are looking for a team or a company that specializes in reverse engineering node.js apps from binary to ASCII. This project will be paid on an hourly basis with a bonus after successful completion. Requirements: Extensive experience in reverse engineering node.js apps Proficient in binary to ASCII conversion Strong problem-solving skills Ability to work independently and meet deadlines If you meet these requirements and are interested in this project, please send us your portfolio and hourly rate. We look forward to working with you! Note: This job posting is exclusively for freelancer.com and we will only consider applications submitted through this platform."

    €9 - €37 / hr
    À la une Scellé LDN
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    java project S'est terminé left

    isc programming in java An encoded text can be decoded by finding actual character for the given ASCII code in the encoded message. Write a program to input an encoded text having only sequence of ASCII values without any spaces. Any code or value which is not in the range 65-90 (A – Z) or 97-122 (a – z) or 32 (for space) will be ignored and should not appear in the output message. Write a program to accept a CODE which contains only digits (0 to 9). Display an error message if the code contains any other character/s. Perform the following tasks: (a) Decode the encoded text as per the above instructions (b) The first alphabet of each word must be changed to UPPER case and the remaining alphabets to lower case (c) Any consecutive sets of code 32 will be take...

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    Understanding of FPGA for a report S'est terminé left

    I want someone who understands FPGA, Vivado, Verilog, VHDL etc for a report

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    Hi, How are you doing. I am looking for electrical engineers to work on multiple tasks in following areas: • Embedded C Programming. • VHDL/Verilog, LABView/ Multisim/PSPICE • Network Simulator NS2/NS3 • Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC and STM32. • IDEs like Keil MDK V5, ATmel studio and MPLab XC8. • PLCs / SCADA • PCB Designing-Proteus, Eagle. • IOT Technologies like Ethernet, GSM GPRS. • HTTP Restful APIs connection for IOT Communications. I am looking for long term work relationship. New freelancers are warmly welcomed. Important Note: I need dedicated freelancers who strictly follow the deadline and give me good quality work without any plagiarism.

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