A Freelancer with skills in digital logic design is needed to write a small program for a CPLD device using WinCUPL. Atmel/Microchip devices would be used. The CPLD will manage clocking a fixed byte stream into a FIFO ic. The byte stream will not pass through the CPLD device. The program should be simulated and verified. Please see attachments and feel free to offer suggestions.
I have 1.25 Mbps data on an avalon-ST interface to be transferred to the HPS then to the ethernet port on DE1-SOC board. The data are on 24 channels of 24bit samples. I need you to explain the work to me in case I need to modify it or change the platform. My project which collects the data is attached. The top-level file is i2s_dsp
My project require someone knowledgable in the area of wsn. The main Idea would be enhancing a currently existing routing protocol in wireless sensor nodes, the code can be done in any language, I prefer Matlab and or c++ using omnet++ simulator
Circuit board designer required for FPGA board with the following specifications. PCI-Express Xilinx Kintex 7 FPGA 50a VCCINT power to FPGA JTAG port (Possible option of 2 x DDR3 SODIMM RAM Slots)
Cu ajutorul placii de dezvoltare Nexys 4 DDR dorim citirea datelor receptionate de o placa ce contine o fotodioda. Semnalele primite sa le afisam si sa le prelucram ulterior cu ajutorul unor algoritmi de filtrare pentru a obtine la final niste date valide.
I am currently working on some small project need to implement an image processing on FPGA, which may include patterns detection after red color segmentation and recognizing the detected patterns....the image size is 240x240 which has some patterns covered in red color
This project need to implement the several LVDS interface between Xinix Atix and a sensor buffer This project is completed after simulating transfer (Buffer content ==> FPGA RAM content) This is the testing project, so that, you can get more projects after completing this. If you have experiences, you can complete within a few days. Deliverables: Verilog & buffer frame communication si...
I have a de1-soc fpga board ([se connecter pour voir l'URL]) for the detail. currently i have difficulty id generating code for image processing for my image. I have a completed matlab code that include the image and filtering kernel. I need the code to run into my fpga board.
We're looking for someone with experience is sending data from an FPGA to a PC via a FT601 chip (made by FTDI) and saving the data to a binary file on the PC side.
Preciso de um profissional com experiência em programação para máquinas POS (point of sale) para criar um sistema de emissão de ingressos. Necessário sistema web para gerenciar as vendas. Possibilidade de pagamento na POS via cartão de crédito/débito. Aguardo interessados para combinar.
1. Vivado HLS fixed code optimization 2. Introduction of parallelism and pipeling 3. c-simulation, synthesis and RTL-C cosim verification 4. IP generation in Vivado HLS 5. Intergration of IP generated in HLS in Verilog code
FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design
FPGA based VHDL code of control system device, the design should be handwritten, not generating code. The FPGA design must have the std logic data type of the inputs and the outputs and S-Fixed numbers of the entire control design.