Assemblyx86 verilog vhdl jobs

Filtrer

Mes recherches récentes
Filtrer par :
Budget
à
à
à
Compétences
Langues
    État du travail
    2,720 assemblyx86 verilog vhdl travaux trouvés au tarif de EUR

    Nous avons la possibilité de produire des ASIC en quantité, nous avons une usine en chine, et nous voulons joindre la vague des miner de crypto monnaie .. Nous recherchons un passionné qui saura designer l'ASIC pour miner différente monnaie etc .. Merci

    €5010 (Avg Bid)
    €5010 Offre moyenne
    1 offres

    je suis suposé faire un projet en VHDL de A jusqu'à Z , je manipule bien le logiciel je peux decrire aussi que simuler et implémenter sur une carte FRGA , mais je me crois pas au niveau pour bien choisir un sujet ( je suis débutant , je connais pastrop sur ce que peut faire ce merveilleux logiciel ) aussi que faire l'architecture globale du projet

    €130 (Avg Bid)
    €130 Offre moyenne
    3 offres
    Systemverilog-UVM tracer S'est terminé left

    Tracer using System verilog & UVM

    €249 (Avg Bid)
    €249 Offre moyenne
    4 offres
    verilog project mips S'est terminé left

    MIPS ALU design

    €26 / hr (Avg Bid)
    €26 / hr Offre moyenne
    1 offres

    Verilog digital logic deisgn simple work

    €20 (Avg Bid)
    €20 Offre moyenne
    18 offres

    I have Altera Verilog source code. This is crosspoing from Altera. Add a special feature (essential) to enable any one input (DI) to connect simultaneously to ALLoutputs (DO). Likely part would be EPM570T100I5. You can get source code follow link. [se connecter pour voir l'URL]

    €40 (Avg Bid)
    €40 Offre moyenne
    16 offres
    i neeb vhdl project S'est terminé left

    i need vhdl project for fpga bord i need skeleton and can move

    €21 (Avg Bid)
    €21 Offre moyenne
    14 offres

    I have a simple Verilog project. This is very simple. I attached a Logic diagram. Please reference this. Thanks for advance.

    €20 (Avg Bid)
    €20 Offre moyenne
    22 offres
    FPGA ALTERA - VHDL project S'est terminé left

    Need help developing a face detection system with the DE2-115 board and OV7670. I already developed the code for the face detection but in MatLab.

    €189 (Avg Bid)
    €189 Offre moyenne
    14 offres
    Simple Verilog Program. S'est terminé left

    I want to Verilog programmer. This job i This is very simple. I attached image for logic. You can write code on QuartusII. and then the code must be compiled. Please check image and place bid. Thanks.

    €19 (Avg Bid)
    €19 Offre moyenne
    17 offres

    i want to realize the transfer function on fpga so any one with knowledge of vhdl and quartus tool can bid Thank you

    €32 (Avg Bid)
    €32 Offre moyenne
    6 offres
    vhdl project S'est terminé left

    I need you to implement a vcdl design project

    €62 (Avg Bid)
    €62 Offre moyenne
    16 offres
    Verilog design project S'est terminé left

    Verilog and Quartus based programming. The project requires a working alarm clock with certain specifications to be met when certain switches are activated.

    €18 / hr (Avg Bid)
    €18 / hr Offre moyenne
    20 offres

    ...in der Digital- / Analotechnik - Kenntnisse von Simulations- und Prüfumgebungen - Kenntnisse mit technischer Dokumentation/Nachweisführung. Technisch: - OrCAD, PSpice, FPGA/VHDL, C++ - DO-254, MIL-STD-1553...

    €5026 (Avg Bid)
    €5026 Offre moyenne
    3 offres
    Verilog program counter S'est terminé left

    Program counter to be simulated with testbench and implemented on De0-cv fpga. Please see file for exact specificiations and criteria.

    €113 (Avg Bid)
    €113 Offre moyenne
    19 offres

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period

    €105 (Avg Bid)
    €105 Offre moyenne
    13 offres
    Tic Tac Toe in VHDL S'est terminé left

    I am looking someone who can fix the errors of the game tic tac toe in VHDL for DE2-115 and prepare report.

    €64 (Avg Bid)
    €64 Offre moyenne
    4 offres
    System Verilog Trainer S'est terminé left

    We are looking for a System Verilog Training for few Engineers in our premises.

    €1704 (Avg Bid)
    €1704 Offre moyenne
    5 offres

    I need you to develop some VHDL designs for me. I would like this software to be developed in VHDL hardware descriptive language. With a  VHDL design and simulation

    €216 (Avg Bid)
    €216 Offre moyenne
    3 offres

    Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit

    €86 (Avg Bid)
    €86 Offre moyenne
    8 offres

    this is my brief description of my project and please only serious people who would like to work and help me make a bid MY FPGA board is DEO nano SOC CYCLONE 5 1. reading an anolog signal (adc is available on board )ltc2308 is the adc which is available on fpga a board 2. realization of PID controller on FPGA 3. realization of process module on fpga (simple equation as to be realized here i.e P...

    €314 (Avg Bid)
    €314 Offre moyenne
    2 offres

    firstly i am posting this second time because the guy called https://www.freelancer.com/u/ahmedmohamed85?ref_project_id=17168255 (Ahmedmohamed85) has showed is arrogance and negligence after accepting my project and asked me to create a milestone and cancelled it and made me to wait for 3 days without answering please guys kindly dont get fooled with such experienced guys and ruin your money and t...

    €50 - €120 / hr
    €50 - €120 / hr
    0 offres

    i will explain in brief when we discuss

    €14 / hr (Avg Bid)
    €14 / hr Offre moyenne
    12 offres
    System Verilog Project 5 S'est terminé left

    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

    €104 (Avg Bid)
    €104 Offre moyenne
    21 offres
    VHDL coding S'est terminé left

    HDL coding from block diagram and pseudo algorithm

    €21 (Avg Bid)
    €21 Offre moyenne
    5 offres
    Alarm clock Verilog S'est terminé left

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

    €158 (Avg Bid)
    €158 Offre moyenne
    15 offres
    Project using VHDL for FPGA S'est terminé left

    Develop a musical bell that will play a selected and programmed song in the FPGA.

    €74 (Avg Bid)
    €74 Offre moyenne
    4 offres

    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

    €74 (Avg Bid)
    €74 Offre moyenne
    5 offres
    Verilog Coding expert needed S'est terminé left

    Hello, I need some help with Verilog coding. I already have the code but Im having errors and cant compile it. Also, I need hepl with implementing testbench. Teamviewer required to debug the code and I can send you the document to take a look at the project.

    €91 (Avg Bid)
    €91 Offre moyenne
    11 offres

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow)...implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    €114 (Avg Bid)
    €114 Offre moyenne
    7 offres
    VHDL expert needed S'est terminé left

    Expert in VHDL needed to work on a code

    €11 / hr (Avg Bid)
    €11 / hr Offre moyenne
    14 offres
    Code Conversion S'est terminé left

    Small project to write in VHDL

    €95 (Avg Bid)
    €95 Offre moyenne
    24 offres

    - Development Environment Tool : Xilinx Vivado and SDK Latest version Device : Xilinx Zynq7045 HDL : Verilog HDL Required IP Module :HDMI_RX, HDMI_TX Using PG235 [se connecter pour voir l'URL] Using PG236 [se connecter pour voir l'URL]

    €110 (Avg Bid)
    €110 Offre moyenne
    3 offres

    Implement an algorithm in vhdl done in Matlab using System Generator

    €83 (Avg Bid)
    €83 Offre moyenne
    11 offres

    ...5ms / 20ns = 125000 dcycle_mid = (dcycle_max – dcycle_min) / 2 = 75000 Για την περιστροφή του servo θα χρησιμοποιήσουμε τα δύο κουμπιά π&omic...

    €34 (Avg Bid)
    €34 Offre moyenne
    1 offres

    1. Create a top level VHDL file for the project. VHDL code should be well formatted and commented. 2. Add two instantiations of a sync counter to the top level that are customized for the horizontal and vertical sync signals 3. Adapt the tesbench from homework 2 to simulate the top level file. Simulations should be annotated to depict events important

    €66 (Avg Bid)
    €66 Offre moyenne
    6 offres

    Hello, I have the complete knowledge of languages like shell, perl, python, verilog and system verilog.

    €62 (Avg Bid)
    €62 Offre moyenne
    1 offres
    Project for Iqra Software .. S'est terminé left

    Hi Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members ar...Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members are experienced with Verilog FPGA programing?

    €36 / hr (Avg Bid)
    €36 / hr Offre moyenne
    1 offres

    Necesito hacer un programa en VHDL de un reloj (formato 24hs), con cronometro y con alarma. Cuando cambio a cada uno. no se debe perder la cuenta de la hora, cronometro o la alarma seteada. El reloj, la alarma y el cronometro se debe poder cargar/modificar manualmente. Detención y reinicio del cronometro. Cuando la hora del alarma coincida con el clock

    €155 (Avg Bid)
    €155 Offre moyenne
    1 offres
    Image encryption S'est terminé left

    I need image encryption using verilog on FPGA board

    €690 (Avg Bid)
    €690 Offre moyenne
    13 offres

    I need the services of a Verilog/ Finite State Machine, Logic Control Designer/ Programmer. Good Logic synthesis is required which is basically conversion of a high-level description of design into an optimised gate-level or FSM representation. Regards,

    €25 (Avg Bid)
    €25 Offre moyenne
    16 offres

    I need verilog code and test bench for implementing Reed Solomon (450,406) encoder and decoder.

    €484 (Avg Bid)
    €484 Offre moyenne
    11 offres
    €8 Offre moyenne
    1 offres
    Project for Manoj J. S'est terminé left

    Need to Develop one VHDL Program. more details will be provided on chat.

    €18 (Avg Bid)
    €18 Offre moyenne
    1 offres
    Project for Miaomiao G. S'est terminé left

    Implement a program on VHDL

    €26 (Avg Bid)
    €26 Offre moyenne
    1 offres
    hardware Design S'est terminé left

    vhdl code for wireless adhoc network and its implementation in FPGA,

    €121 (Avg Bid)
    €121 Offre moyenne
    4 offres
    Motor Control S'est terminé left

    Convert C code to VHDL for BDLC, see attached datasheet. C code is available from TI website (or I can provide). Need to convert code, which is based on document into VHDL. Deliverables: VHDL code + working testbench + block diagram Need to be knowledgeable in Motor Control, C/C++ and VHDL.

    €357 (Avg Bid)
    €357 Offre moyenne
    15 offres

    Verilog BMI calculator Due date: 26.08.2018

    €69 (Avg Bid)
    €69 Offre moyenne
    1 offres
    help with VHDL Question S'est terminé left

    Help with a few questions on VHDL

    €23 / hr (Avg Bid)
    €23 / hr Offre moyenne
    14 offres