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    3,069 assemblyx86 verilog vhdl travaux trouvés au tarif de EUR

    écrire un code vhdl , pour DE0 nano , permettant de lire la température a partir d'une entrée analogique avec un LM19 et en sortie il faut emmètre des son avec un buzzer ( différent fréquence en fonction de la température )

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    Nous avons la possibilité de produire des ASIC en quantité, nous avons une usine en chine, et nous voulons joindre la vague des miner de crypto monnaie .. Nous recherchons un passionné qui saura designer l'ASIC pour miner différente monnaie etc .. Merci

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    je suis suposé faire un projet en VHDL de A jusqu'à Z , je manipule bien le logiciel je peux decrire aussi que simuler et implémenter sur une carte FRGA , mais je me crois pas au niveau pour bien choisir un sujet ( je suis débutant , je connais pastrop sur ce que peut faire ce merveilleux logiciel ) aussi que faire l'architecture globale du projet

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    Systemverilog-UVM tracer S'est terminé left

    Tracer using System verilog & UVM

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    verilog project mips S'est terminé left

    MIPS ALU design

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    Hi. I have a Terasic De1SoC and would like to learn how to use it. I am completely knew and have seen content from a similar project and interested on these topics About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design Implementing various encryption and decrypt algorithms SystemVerilog VMM Methodology OVM Methodology UVM Methodology I have C programming background

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    I need vhdl code for signal processing. I need 256 point fir filter and 4096 point fft. create bid, many experience in signal processing. chatting discussing in detail

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    Build a CNN 4 jours left

    Hi, I need : * CNN IN FPGA using my mac unit? *Verilog *MNIST DB

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    Need example code de-10 S'est terminé left

    I need a sample code on DE-10 code for utilizing the FPGA-HPS bridge with more emphasis on hardware acceleration. (C ,VHDL prefferd /Verilog). I am trying to explore the functionality where I can write some data from HPS to the FPGA. let the FPGA process it and HPS read back the result. I need to see some processing happening in FPGA on request from HPS . IT could be as simple as AND impleme...

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    Scope includes the programing (vhdl) for the measurement and of AC voltage, currents, Power (active, reactive and apparent power) and Power Factor in FPGA (Spartan-6). Interfacing ADC and sensors with FPGA for current and voltage measurements. It also includes the display of measured parameter on LED display which is inbuilt on board). This is the brief requirement, interested people may contact ...

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    More details will be shared via chat

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    More details will be shared via chat

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    Implementation of Fractional-order function (S^e) on FPGA using VHDL. I don't want imaginary freelancer, please, please.

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    Complex Signal Mixer VHDL S'est terminé left

    Design and Document a VHDL Complex Mixer • Design should contain two 11-bit complex NCOs (Numerically Controlled Oscillator): • Assume clock freq of 100MHz • NCO #1: 11MHz • NCO #2: 18MHz • Design a complex multiplier component • Multiply the outputs of NCO #1 and #2 • Write the outputs of the NCOs and Complex Multiplier to a text file Theory of operation Detai...

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    Implementation of Fractional-order function (S^e) on FPGA using VHDL. (I need to fix my code only) I don't want imaginary freelancer, please.

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    Complete few tasks on Verilog software

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    Code on Verilog S'est terminé left

    Complete few tasks on Verilog software

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    Have several ways to effectively reduce sidelobe the ACAR. In order to overcome the contradictions of weight-based processing techniques and ensure high resolution, I intend to use the NLFM signal. I want to do all the processing with one FPGA without using any other block like DDS. There is an expectation that a signal generator for NLFM signal with resolution of 2 ^ 32 and FIR code for correspon...

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    HW Help w/ Verilog & Vivado S'est terminé left

    Hey looking for some help with some introductory logic building using Verilog code on the vivado software. Also Its for basys3. It’s really elementary and if you know how to use vivado this should be quick and easy money for you. Thanks

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    Compile a verilog code S'est terminé left

    I need help in compiling a verilog code. I have already built a code that runs on a platform but when i run it on multisim, it gives me errors. I need an expert to guide me with this

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    Simplistic Matrix engine S'est terminé left

    I want to create a simple CPU the do some mathematics logic between two matrices using Verilog code

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    Hi, I need to emulate a crystal oscillator circuit (attached) based on wave digital filter (WDF). Basically we aim to have WDF emulation that match a Spice simulation (e.g. in Cadence). I Already have the circuit simulated in Cadence (the output attached) . Attached, my circuit (Crystal Oscillator) schematic that needs to be mapped to WDF along with its output waveform, you will notice that there ...

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    Project for Jin Q. S'est terminé left

    Hi Jin :) I have an assignment which I'm not able to get through..I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display and when the val...

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    Project for Nick B. S'est terminé left

    Hi Nick :) I have an assignment which I'm not able to get through..I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display and when the va...

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    Project for Jin C. S'est terminé left

    Hi Jin :) I have a small doubt with the VHDL code I have and I just need to fix it.. It won't take more than 15 mins for you hopefully. The code emulates a vending machine on an ALTERA DE2-115 Board and the push buttons simulate an insertion of a coin..and the incremented value is displayed on the 7 segment display..however my code is glitchy...if you could help me fix it it'd be a life...

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    Temperature sensor and FPGA S'est terminé left

    Need to write VHDL program for Genesys 2 board for connecting a temperature sensor to xadc pin and display it in external LCD board

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    I have a task on verilog and i want someone who is experience on it to help me with it. Please bid only if you know youre an expert. I will share details with interested freelancer. Budget is limited, hiring will be on a weekly basis

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    Hi, I need a basic example of a state machine in VERILOG. We need to find the pattern "100" using machine states. We have 4 states: S0: Initial state S1: If 1 is found S2: If 0 is found S3: If 0 is found Encoding: S0: 00 S1: 01 S2: 11 S3: 10 Transition: Actual state / Input / Next state 00 - 0 - 00 00 - 1 - 01 01 - 0 - 11 01 - 1 - 01 11 - 0 - 10 11 - 1 - 01 10 - 0 - 00 10 - 1 - 01 T...

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    Handson training required on Xilinx Zc-702 including device programming in vhdl and its interfacing with perepherels like ADC, DAC, Memory etc.

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    FPGA and Vhdl expert needed S'est terminé left

    I have problem in "fpga" I can't how to interface between power stage card and "fpga" card Can you write program in "vhdl" language?

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    Wanted Online FPGA Tutor S'est terminé left

    To Teach : About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design SystemVerilog VMM Methodology OVM Methodology UVM Methodology

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    FPGA Development S'est terminé left

    More than 2 years of experience in FPGA design and development area. Candidate should have working Industry experience in below skill set:- •Working experience to process received frequency chirplet data using FPGA and to transmit processed data by interfacing FPGA with Radio Frequency (RF) transceiver module ADRV9009 and 10 Gigabit Ethernet Media Access Controller (10GEMAC). •Working ...

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    Embedded systems designers S'est terminé left

    Needs to hire 3 Freelancers We are a small and growing company offering consulting and engineering services in many different areas of industry. Here you can find more about us: [se connecter pour voir l'URL] In order to enforce our team, we are seeking embedded systems designers with experience in the following domains: * PCB design (Altium Designer, Eagle, KiCAD, PCAD...) * Firmware design...

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    Hi, We are looking for an experienced electronics engineer and software engineer, The project is to design a smart Home Cinema controller, the aim is to send data to a database, reading and writing data of different Video Projectors, Amplifiers, and many more devices via HDMI, USB, RS232, Ethernet, IR and many more. You will conceptualise the electronics and software for the system. We are stric...

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    Filtro de 3 bandas en vhdl S'est terminé left

    Implemente un sistema de ecualización en tiempo real de tres bandas (bajos, medios y altos) en el FPGA de xilixn. Desarrolle los tres filtros necesarios para el ecualizador, los puede establecer en matlab o labview. Una vez definidos los coeficientes del filtro impleméntelos en el FPGA (a través de Matlab, Laview o Multisim). Se establece un bonus de 4 puntos para el grupo qu...

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    Build a neural network S'est terminé left

    Hi, I need : * ANN IN FPGA using my mac unit? *zybo-zynq-7000-arm-fpga-soc-trainer-board/ *verilog *MNIST

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    Counter in VHDL S'est terminé left

    Create a design with two counters and a 7-Segment Display • The first “Fast Counter” should count up 0 -> 49999999 and then reset to zero • When the Fast Counter reaches 49999999 it should output a single pulse on the “o_max_val” output to the second counter • The second counter (4-bit) counter should include a “i_count_enable” input, connected...

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    8 bit processor S'est terminé left

    fix bug in verilog hdl for 8 bit

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    Design an 8-bit microprocessor using Verilog HDL by using Structural Verilog modelling. The individual components can be designed using behavioral modelling. Mandatory components: Instruction Memory Register File Data Memory ALU Control Unit Multiplexers Sign extend unit Program counter The Register File has two registers R0 and R1. Design the program counter and instruction memory such that input...

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    Enable all the listed hardware as the attached image. (2xMarvell ETH, MIG-DDR3, SD, QSPI Flash, PS-DDR3, uart) 2. Install Configured Petalinux, with Python, Flask, numpy, Pillow, littleCMS . Boot with QSPI (We will access this board on the Ethernet, make ETH0 DCHP and ETH1 Fixed @ [se connecter pour voir l'URL]) 3. Display JPEG/TIFF image file from SD in webpage. 4. Add one function ...

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    I have the algorithm of what I want to implement, I just need help a second eye to help me understand how to implement it.

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    Implementation of Fractional order function (S^e) on FPGA using VHDL. I don't want imaginary freelancer, please.

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    I need a simple VHDL program for measuring the time between two input signals. The VHDL program should be in structural code and should includes modules like Counter, BCDtoASCI, UART and FStateMachine + top level. I need also for every module and for the hole program testbenches.

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    RS-FEC 198,194 verilog code S'est terminé left

    VLSI design for Reed Solomon FEC for 198,194 including documentation and explanation. Verilog files and simple testbench to prove the design. ASIC

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    Hey, I have working project in simulation that when I try to run it on board it doesn't work. I need someone with that board or that have familiar board to notice if there is problem with my code.

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    This includes the development of vhdl code for PWM generator, PID controller, flux estimator etc. Training would be web based on Skype or webex.

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    I am looking for someone who can design a FPGA based hash algorithm including blake bmw sha512 skein luffa shavite simd echo hamsi shabal whirlpool and jh. Developer need to complete FPGA bitstream, and provide verilog source codes.

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    Build me verilog project S'est terminé left

    I want to implement a paper using verilog coding.. Kindly review paper before biding

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