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    2,208 vhdl vga virtex2 travaux trouvés au tarif de EUR

    écrire un code vhdl , pour DE0 nano , permettant de lire la température a partir d'une entrée analogique avec un LM19 et en sortie il faut emmètre des son avec un buzzer ( différent fréquence en fonction de la température )

    €31 (Avg Bid)
    €31 Offre moyenne
    2 offres

    Nous avons la possibilité de produire des ASIC en quantité, nous avons une usine en chine, et nous voulons joindre la vague des miner de crypto monnaie .. Nous recherchons un passionné qui saura designer l'ASIC pour miner différente monnaie etc .. Merci

    €4960 (Avg Bid)
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    1 offres

    je suis suposé faire un projet en VHDL de A jusqu'à Z , je manipule bien le logiciel je peux decrire aussi que simuler et implémenter sur une carte FRGA , mais je me crois pas au niveau pour bien choisir un sujet ( je suis débutant , je connais pastrop sur ce que peut faire ce merveilleux logiciel ) aussi que faire l'architecture globale du projet

    €128 (Avg Bid)
    €128 Offre moyenne
    3 offres

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like Read ...disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

    €353 (Avg Bid)
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    2 offres

    In ready projekt on vhdl (tic tac toe game) I need to add state od the gamę on LCD [login to view URL]

    €27 (Avg Bid)
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    5 offres

    I need to write a VHDL code for transfer data from 2 zedboard using ethernet without using a zynq-processor

    €177 (Avg Bid)
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    12 offres

    I have a short project to do for an Altera 5M160Z CPLD (160 LE). This board has a 16-bit bus from a MCU and 8 control lines and output to a 10-pin port. What I need is a VHDL project (Quartus) that will implement a custom full duplex parallel to serial design. Development using simulation is fine.

    €16 / hr (Avg Bid)
    €16 / hr Offre moyenne
    11 offres

    add memory protection into the operating system, This project needs both hardware and software knowledge, you will be creating / implementing OS functions on the PicoBla...hardware and software knowledge, you will be creating / implementing OS functions on the PicoBlaze, programming in assembler. You may also need to modify the hardware using VHDL.

    €424 (Avg Bid)
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    11 offres

    Hello guys I will need these simple tasks for $10USD the deadline is today 8 September. Description In C language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory). I would like comments on the code and the new resulting image as deliverables. I attach the image table in the files section. Thank you a lot...

    €94 (Avg Bid)
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    1 offres

    Hello guys I...cache memory). I would comments on the code and the resulting image as deliverables. 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works. Again comments on the code please. P.S.: 8 by 8 vhdl integer divider I attach the image table in the files section. Thank you a lot for your bidding :)

    €21 (Avg Bid)
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    3 offres

    Hello guys I will ...language, i will need embedded a median filter that I need to pass after a FPGA microblaze with image data (128x128) (with and without cache memory) 2) I need just a divider in vhdl language to pass through and confirm with numbers that it works I attach the image table in the files section. Thank you a lot for your bidding :)

    €24 (Avg Bid)
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    3 offres

    I need help with the structural in Xilinx. I will give you full details. Regards

    €20 (Avg Bid)
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    24 offres

    ...looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but having

    €32 (Avg Bid)
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    112 offres

    Hi, my name is Paride, nice to meet you. i have got your conctact from Alessandro, a classmate. I am working on a easy Vhdl project, i already wrote all the code, the simolulation is working, but i need your help for two fast tasks: • I need to assign the pins on my FPGA, i can't find the correct pin of 2 serial signals. • i need you to check if the

    €49 (Avg Bid)
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    1 offres

    Implement an AD2949 IC input block and some more

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    12 offres

    I want a content writer who knows digital design or digital electronics and vhdl subjects very well.

    €71 (Avg Bid)
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    21 offres

    Hi there! I'm based in Ahmedabad, India. This project is related to lightweight cipher, cryptography. I have attached a pdf containing information relevant to this project w...design so that I can perform power analysis on it. Need the code properly working in two days. I looking for a Clock based implementation on existing design Language used : VHDL

    €47 (Avg Bid)
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    4 offres

    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be found...clock based design so that I can perform power analysis on it. Need the code properly working in two days. Note: Clock based implementation on existing design Language used : VHDL

    €26 (Avg Bid)
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    ...uuid=f5dbdd1e-d9fa-4b3d-b98a-2870d47fd3d2' -smp '8,sockets=2,cores=4,maxcpus=8' -nodefaults -boot 'menu=on,strict=on,reboot-timeout=1000,splash=/usr/share/qemu-server/[login to view URL]' -vga std -vnc unix:/var/run/qemu-server/[login to view URL],x509,password -cpu kvm64,+lahf_lm,+sep,+kvm_pv_unhalt,+kvm_pv_eoi,enforce -m 16512 -vnc 0.0.0.0:100 -device 'pci...

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    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    €332 (Avg Bid)
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    3 offres

    Hi there! I'm based in Hyderabad, India. This project is related to cryptography. I have attached a pdf containing information relevant to this project which can be ...individual modules are successfully executing but the final result doesn't appear which you can help me in debugging the same ) Note: Problem in debugging the code Language used : VHDL

    €134 (Avg Bid)
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    9 offres

    expert on VHDL is need for a project on digital thermostat. This is a simple task. expert only should bid

    €62 (Avg Bid)
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    20 offres

    build a communication block in VHDL at Xilinx environment

    €342 (Avg Bid)
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    14 offres

    Implement Communication VHDL Comm port on Xilinx FPGA part

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    16 offres

    i need explained how to do impedance matching when making transmission cables for cvbs/vga signals to tv/lcd/monitors pc

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    7 offres

    i have a task related to Communication VHDL Xilinx, i will share the details in chat.

    €98 (Avg Bid)
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    19 offres

    i need vhdl project for fpga bord i need skeleton and can move

    €20 (Avg Bid)
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    14 offres

    Need help developing a face detection system with the DE2-115 board and OV7670. I already developed the code for the face detection but in MatLab.

    €187 (Avg Bid)
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    14 offres

    i want to realize the transfer function on fpga so any one with knowledge of vhdl and quartus tool can bid Thank you

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    6 offres

    I need you to implement a vcdl design project

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    16 offres

    Software Engineer with Experience in C++, Data login, A/D Converters, DAC , HMI, LAN data collection , hardware knowledge deisred enougj to gnerate schematic vga, rs232,, Microprocessor ARM, Raspberry Pi or Beagle black experience a plus.

    €1235 (Avg Bid)
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    13 offres

    ...in der Digital- / Analotechnik - Kenntnisse von Simulations- und Prüfumgebungen - Kenntnisse mit technischer Dokumentation/Nachweisführung. Technisch: - OrCAD, PSpice, FPGA/VHDL, C++ - DO-254, MIL-STD-1553...

    €4924 (Avg Bid)
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    3 offres

    I am looking someone who can fix the errors of the game tic tac toe in VHDL for DE2-115 and prepare report.

    €64 (Avg Bid)
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    4 offres

    I need you to develop some VHDL designs for me. I would like this software to be developed in VHDL hardware descriptive language. With a  VHDL design and simulation

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    this is my brief description of my project and please only serious people who would like to work and help me make a bid MY FPGA board is DEO nano SOC CYCLONE 5 1. reading an anolog signal (adc is available on board )ltc2308 is the adc which is available on fpga a board 2. realization of PID controller on FPGA 3. realization of process module on fpga (simple equation as to be realized here i.e P...

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    2 offres

    firstly i am posting this second time because the guy called https://www.freelancer.com/u/ahmedmohamed85?ref_project_id=17168255 (Ahmedmohamed85) has showed is arrogance and negligence after accepting my project and asked me to create a milestone and cancelled it and made me to wait for 3 days without answering please guys kindly dont get fooled with such experienced guys and ruin your money and t...

    €49 - €119 / hr
    €49 - €119 / hr
    0 offres
    €14 / hr Offre moyenne
    12 offres

    HDL coding from block diagram and pseudo algorithm

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    Develop a musical bell that will play a selected and programmed song in the FPGA.

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    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow)...implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    €112 (Avg Bid)
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    7 offres

    Expert in VHDL needed to work on a code

    €11 / hr (Avg Bid)
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    14 offres

    Small project to write in VHDL

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    24 offres

    Implement an algorithm in vhdl done in Matlab using System Generator

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    ...5ms / 20ns = 125000 dcycle_mid = (dcycle_max – dcycle_min) / 2 = 75000 Για την περιστροφή του servo θα χρησιμοποιήσουμε τα δύο κουμπιά π&omic...

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    1. Create a top level VHDL file for the project. VHDL code should be well formatted and commented. 2. Add two instantiations of a sync counter to the top level that are customized for the horizontal and vertical sync signals 3. Adapt the tesbench from homework 2 to simulate the top level file. Simulations should be annotated to depict events important

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    6 offres

    Necesito hacer un programa en VHDL de un reloj (formato 24hs), con cronometro y con alarma. Cuando cambio a cada uno. no se debe perder la cuenta de la hora, cronometro o la alarma seteada. El reloj, la alarma y el cronometro se debe poder cargar/modificar manualmente. Detención y reinicio del cronometro. Cuando la hora del alarma coincida con el clock

    €153 (Avg Bid)
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    1 offres

    Need to Develop one VHDL Program. more details will be provided on chat.

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    1 offres

    Implement a program on VHDL

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    1 offres