hey hi, This is manikanta i am an undergraduate student at VIT Vellore in the domain of electronics and communication engineering and i currently working as a RTL Design & Verification intern at Raiton semiconductor.
i had very good knowledge in VLSI, Verilog, digital electronics, System Verilog, UVM(universal verification methodology)
i have good knowledge in using the tools like modelsim, questasim, Xilinx vivado, quartus prime, Aldec riviera pro,..etc.
i feel i will be really useful for your work and i will make sure, i will complete the work within the deadline.