digital alarm clock using VHDL

Dear sir, I already have the DE2 board, i have more than 7 years experience in digital design using VHDL please message me so that we can discuss project details

I have had more than 3 years experiences on FPGA Design using Verilog and VHDL: - FPGA's Xilinx and Altera. - MicroBlaze, Embedded system design on FPGA of Xilinx. - FPGA, VLSI Implementation of DSP System( Matlab or C, C++, algorithm). - Digital logic design. - Some previous projects: + Matlab and FPGA Implementation of a License Plate Recognition System on FPGA Spartan-6 of Xilinx. + FPGA Implementation of a Fall Detection System on Virtex-5 Xilinx FPGA. + FPGA Implementation of a Fingerprint Identification System on Virtex-5 Xilinx FPGA. + VLSI Implementation of image/video compression in wavelet domain using DWT and SPIHT algorithm + Penalty football game on VGA DE2-70, DE2 Altera + AES 128, 256, 192. + MIPS Single-cycle, Pipeline processor.

I can help you right away! I have 8 years experience with vhdl and fpga! I worked for TTTech and Infineon and Philips as a digital design engineer! I can help you right away! Please send me a message to talk more about your project! Also the price is negotiable! Have a nice day!

i am an electrical engineer and i also have experience using FPGA board and verilog language which makes me suitable candidate for this job.

A proposal has not yet been provided

Hi, I am a PhD student @ University of Califonia. I have 6+ years FPGA and VHDL experiences. I can finish this job with 100% guarantee and good documentation.

I have worked on designing IP using verilog on Altera FPGA. I have also worked on optical communication where I used 8 bit ADC for analog to digital conversion. I have DE2-115 board and I can promise you that I will give me 100% completing this project.

I, Keyur Mahant working in One of the leading University of India as Asst. Professor in Electronics and Communication Engg. And Space Technology Center as Project Scientist in which, I am working on “Single Event Upset Characterization of FPGA”. In addition I had a one year experience to work with Physical Research Laboratory (PRL), Ahmadabad. In PRL I was working on Chandrayan-2 payload design where I had developed a DAQ for X- Ray florescence for elemental analysis. I had also made a project for Face Recognizance Using PCA in MATLAB. Please send me the details of your project. Currently I am also processing the data of dosimeter UDOS001 using Sparten-3E FPGA and onboard histogram generation using Sparten-3E FPGA with internal memory and external memory.

Dear Employer, I can support you for development of this project. Have earlier worked on this board for small scale projects. Here is my profile summary for your reference: Experience in Digital ASIC/FPGA Design, RTL development, optimization and functional verification, RF Prototype board development and management, Complex IC Packaging. Designed ASIC Digital blocks for CMOS 130nm Transceiver Design Project based on IEEE802.15.4g. Development of part of H.264 Video Standard with the knowledge of complete Video CODEC flow, Image Segmentation algorithms, AHB Bridge, OFDM Module, CORDIC algorithm and JPEG Decoder module. Looking forward to work with you. Thank You Regards Prasanna Choudhary Skype: prasannachoudhary