Altera de2 qsysemplois

...standard off the shelf LCD using RGB interface. In addition, the image will require interpolation while keeping the original aspect ratio. Source device will be provided + timing chart of source. Output LCD + LCD controller datasheet + init code will be provided. Development board will NOT be provided (you should have your own). VHDL is preferred but not obligatory, Verilog can also be used. Altera family devices should be used. Project should be oriented towards low power and low cost since day 1. Information about further requirements (some software features) will be provided later. Please read this before quoting. Please do not quote if you can not complete this project. Please make sure this is something you are able to complete within less than 30 days. The project is...

I got DE2 115 FPGA board and to implement the LOW pass filter using MATLAB simulink.

Hi Freelancers, I have a project I've been working on for the past 2 months- an Altera FPGA control system for a specific application. Although I have knowledge in electrical engineering, I have no qualifications in the field, and thus I’d like a qualified individual to confirm my design, correct any mistakes I may have made, and possibly make the product more economical (e.g. remove components, replace current components with more suitable known variations). The board is based on the Altera Cyclone 2 Platform (EP2C5T144), and involves Comparators, Optoisolators, SRAM, an ADC, an Op-Amp, an EPCS4 Device, and several Buck Converters & Regulators for Power Management. I believe the total evaluation time should be ~3 - 6 hours.

Hi, We want to open a project regarding to a special camera module. The camera module should be sel...special camera module. The camera module should be selectable between area scan and line scan mode. The standard area scan sensors should also be driven as line scan sensor. We want to use standard cmos camera modules as RGB, mono with 2K and 4K horizantal resolutions. During line scan mode we need to reach 25 kHz. Area scan speed can be any 10-30 fps. We will use OS08A20 CMOS image sensor and Altera or Xlinx FPGA. As the milesotones: 1. Creation of camera controller to achive area scan and high speed line scan functions. 2. Sending image over USB 3.0 or Gigabit ethernet 3. Testing The estimated period is max 8 weeks. Can you please inform us your interest and availability. Bes...

Hi, We want to open a project regarding to a special camera module. The camera module should be sel...special camera module. The camera module should be selectable between area scan and line scan mode. The standard area scan sensors should also be driven as line scan sensor. We want to use standard cmos camera modules as RGB, mono with 2K and 4K horizantal resolutions. During line scan mode we need to reach 25 kHz. Area scan speed can be any 10-30 fps. We will use OS08A20 CMOS image sensor and Altera or Xlinx FPGA. As the milesotones: 1. Creation of camera controller to achive area scan and high speed line scan functions. 2. Sending image over USB 3.0 or Gigabit ethernet 3. Testing The estimated period is max 8 weeks. Can you please inform us your interest and availability. Bes...

Hi, We want to open a project regarding to a special camera module. The camera module should be sel...special camera module. The camera module should be selectable between area scan and line scan mode. The standard area scan sensors should also be driven as line scan sensor. We want to use standard cmos camera modules as RGB, mono with 2K and 4K horizantal resolutions. During line scan mode we need to reach 25 kHz. Area scan speed can be any 10-30 fps. We will use OS08A20 CMOS image sensor and Altera or Xlinx FPGA. As the milesotones: 1. Creation of camera controller to achive area scan and high speed line scan functions. 2. Sending image over USB 3.0 or Gigabit ethernet 3. Testing The estimated period is max 8 weeks. Can you please inform us your interest and availability. Bes...

VHDL implemented in altera de2 board

Our group wants to implement a game using altera de2 cyclone ii board. Please see the attached file for the details of the game to be implemented.

Need to Build the FPGA to HPS DMA code in Arria 10 Intel-Altera FPGA

Anexar documentos: Enviar foto de contrato, CPF/RG, Conta bancário, Comprovante de Pagamento e etc Cadastrar Cliente: Cadastro com informações tradicional Gerar Boleto: O cliente consegue solicitar o boleto para pagamento. Obs: após o vencimento, faz o cálculo automático de juros e encargos. Chat Encaminhar o atendimento dos cl...cliente fizer o cadastro terá que enviar aproximadamente 10 fotos e duas filmagens (1* aproximadamente 05 minutos, 2*aproximadamente 02 minutos pelo smartphone, preciso saber com precisão a hora e a data que as fotos e a filmagem foi feita para validar a prestação de serviço. OBS: A fotos e videos não podem ser os dados traicionais que o telefone fornecem, porque se alterar a h...

altera de1 simple project to make temperature controller

altera de1 simple project to make temperature controller

Hello, I have developed the full game in verilog, but I need help with a game over screen to pop up with the player loses all of his lives or a win screen with the player has beaten the game. I will provide you with all the code, mifs, rams, and I just need help to implement the win and game over screens.

El objetivo general del presente proyecto consiste en la realización, verificación funcional y validación experimental de un microcontrolador sencillo basado en un subconjunto de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su validación experimental se realizará en el laboratorio mediante una aplicación sencilla propuesta por cada grupo que haga uso de los recursos hardware disponibles en el módulo de test. El proyecto abarca por tanto los aspectos de verificación funcional, descripción de hardware empleando SystemVerilog, implementación de un sistema digital int...

El objetivo general del presente proyecto consiste en la realización, verificación funcional y validación experimental de un microcontrolador sencillo basado en un subconjunto de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su validación experimental se realizará en el laboratorio mediante una aplicación sencilla propuesta por cada grupo que haga uso de los recursos hardware disponibles en el módulo de test. El proyecto abarca por tanto los aspectos de verificación funcional, descripción de hardware empleando SystemVerilog, implementación de un sistema digital int...

I need someone to write verilog code and also test .do files for a maze game. The program should output to vga. The rules of the game are simple. You start at a point and have to figure out how to get to the exit just like an actual maze. However, there is a monster chasing you and if he catches you, you are dead. The player's movement should not be pixel by pixel but rather, it should keep sliding until it hits the wall(boundary). The movement control should be done through the keys on the FPGA. The maze should have a fully functional non-flickering background, which should be easily be replaced. It should also have a start and game over screen. The work should have lots of comments, documentation, and test (.do) files so that it can be easily understood by a beginner. This should f...

Verilog Task with Vivado and Quartus 2. Should be familiar with schematic design in Altera Quartus 2.

I need some help doing some data erasure using Blancco software. We are familiar with Blancco but not with Sun Oracle. The equipment is in East London. I am looking for someone to tell us how to do it or to do it for us as a freelance or similar. The equipment does not need to be re-used - just purged of all data. What we have two Oracle ZS3-2 devices in a cluster which has 3 storage DE2-24P shelves.

...monitor : HP Compaq LA2205wg, VGA mode 1680x1050-60Hz - OS : Linux distro (Linux Mint). - language : VHDL - IDE : Quartus Prime Lite Edition - Simulations with ModelSim - mini-project : 0) implement a 1680x1050-60Hz mode VGA controller (operating @ 143Hz pixel clock via PLL) 1) store 280x280 8byte/pixel image to on-chip memory (M9k blocks) 2) read image from on-chip memory (using Altera/Intel's RAM-1Port vhdl IP) 3) output image to monitor - issue : the above seems to work fine, *except* that the image has glitches. So something is wrong. I suspect that this is due to the RAM reads and I am not exactly sure how to fix this (from why I read online maybe I'd need to buffer some of the signals, or maybe implement a FIFO... but I do not quite know tbh). ...

Snake Game : 1.) Should run on Altera DE2 Board or on basy3 . 2.) Should Support VGA. 3.)Needed in a 3 days. skills:- verilog software:vivado i need this project in verilog and not in VHDL

Looking for a mentor in advanced FPGA development using Altera Max 10 FPGA board specifically.

I have a short project to do for an Altera 5M160Z CPLD (160 LE). This board has a 16-bit bus from a MCU and 8 control lines and output to a 10-pin port. What I need is a VHDL project (Quartus) that will implement a custom full duplex parallel to serial design. Development using simulation is fine.

I have Altera Verilog source code. This is crosspoing from Altera. Add a special feature (essential) to enable any one input (DI) to connect simultaneously to ALLoutputs (DO). Likely part would be EPM570T100I5. You can get source code follow link. and this is description of cross point matrix. Thank you for advance.

Need help developing a face detection system with the DE2-115 board and OV7670. I already developed the code for the face detection but in MatLab.

Designing an FPGA board for "5CEFA9F27I7N altera cyclone v". A board that include 4 ram sockets, full-size DIMM (desktop pc ram), DDR3. And programming an FPGA crypto miner for this board.

I am looking someone who can fix the errors of the game tic tac toe in VHDL for DE2-115 and prepare report.

Hi! After a few days there are several (9-11 and rising) entry processes charge my website and slowly make my website resource error until I end all processes in putty. Your task would find the cause and eliminate and report the code to me. There are 2 cron jobs total on my site. Let me know if you need any more information. Cpanel: Gyogyito Ly6d4aW31u Thank you! Tib

Preciso de uma planilha que me traga quantos livros cabem em 3 tipos diferentes de embalagens, tendo a possibilidade de incluir novas medidas de embalagens e de livros quando necessário. Os livros possuem na maioria os tamanhos 14x21x03 e 18x11x01, onde apenas a espessura altera. As caixas tem as medida (LxCxA) G 45x31x29, M 43x30x17, P 24x16x08. Na planilha quando eu informar a quantidade de livros ela deve trazer quantos livros (diferentes medidas) cabem em cada modelo de caixa e quantas caixas são necessárias para a quantidade informada, para que eu possa analisar qual dos três modelos será ideal pra que eu armazene os livros.

I have an Altera DE1-SoC developmental board and I need a template project which allows me to transfer about 2kB of settings from the HPS side to the FPGA side. I want to use C on the HPS side to set 2048x 8-bit values which the FPGA can use to synthesize an arbitrary waveform in real-time. The memory can be SDRAM or any other suitable options available on the DE1-SoC board. The template project should include the source code and demonstration of: 1. C script which accepts a tuple in the format e.g, "2047,255" to set a value of 255 (0-255) for the 2047th register (0-2047). 2. Quartus Prime project compatible with Quartus Prime Lite 16.1. 3. Ability to inspect the registers on the FPGA side by setting the toggle switches in binary to indicate the register address, and read...

I am looking for FPGA designer (Altera) with experience in DMA over PCIe.

I need coding VERILOG code for BMI calculation that can be run in Quartus software and burn in ALTERA DE2 board. maximum 80usd

...auto, residencial, vida e previdência privada, a url de cada cotação deve ser obtida de nosso banco de dados, para termos flexibilidade nas manutenções . O app não terá chat interno mas sim, redirecionará a uma ferramenta de chat já existente, esse chat é em php e javascript . O app irá capturar de nosso banco de dados, os dados relativos ao usuário e irá exibi-los caso o usuário deseje poderá altera-los, que tipo de dados ? pessoais e endereço. O aplicativo exibirá os registros das apólices do usuário do app cadastradas junto a corretora, as informações serão inseridas no banco por nossa equipe, logo você desenvolvedor n&...

I need someone who can run digital electronic simulation with Intel/Altera Quartus II v15.0 ( I will provide that) and then implement the simulations on FPGA-Based Digital Circuit: Rainbow RGB LED Driver. Please only contact me if you are 100% capable of the above. I can provide the software but You need to have the equipment.

Design a 3-phase 500Hz FPGA based generator driving a quad-channel DAC (only 3 channels needed) such as the LTC 2624. The overall idea is that; following <RESET> a table of values representing a sine wave shall be stored internally and scan sequentially by the three output stages in a manner that each output is 120 degrees off-phase with each other as shown in the attached image. No other work is needed at this point. I will provide a Xilinx Spartan III demo board made by Digilent (), if necessary and have it shipped to the developer. The developer is welcome to keep the board.

We require a simple oscilloscope project to be implemented using only Verilog code on DE1-SoC board by the latest date of 7th of May as agreed during the chat conversation. This project will comprise of modular Verilog code, fully commented, test-benches for verification and a technical report of the project. Altera Quartus software will be used for the implementation of this project. It is agreed that all of above will be completed at a cost of $210 by 7th of may latest. The oscilloscope developed will take in Analogue readings through the internal ADC on-board, do signal processing and display a continuous waveform through VGA. We require an organised and presentable display screen with waveform scale, and current values shown in text aswell.

A very simple oscilloscope developed using Verilog on Altera software, this project will be based on DE1-SoC Board and is expected to be concluded within a week. Only experienced FPGA engineers please.

I need you to develop some software for me. I would like this software to be developed. I need coding for calculate BMI by using altera DE2 board

Board : Terasic DE10-Lite MAX10 10M50DAF484C7G - 2 push buttons - 10 switches - 6 7-segments - 1 SDRAM module (ISSI IS4216320D) - see for more details about the board Software tool : Altera / Intel Quartus Prime Lite 16.1 Project : create a small, minimalistic, Quartus project to illustrate the use of PLL and SDRAM IP libraries. Description : 1) the user turns on or off each switch and defines a 10bit number 2) the user push the number into the SDRAM by pressing button #1 3) the user reads the numbers pushed into memory into the 7 segments by pressing button #2 Essentially that's it. Need well written, well documented, clean code.

Stepper Motor Controller with DE2 board, write vhdl codes, compilation, and simulation.

In order to do the project, you will need Altera's DE2-115 Board. Please contact me for more info. Prior work with MicroC/OS-II RTOS with the Nios II Processor is an asset.

I want to generate square wave by using verilog on Altera DE1-SoC and MTL2 with changing the frequency and Duty cycle

Assembly and C for Altera. Timers and Interrupts. More details to be provided.

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an automobile tail-light control unit is designed on the Altera board. The automobile has two sets of four tail-lights in a row. For the turn right signal, the right sided tail-lights flash in the sequence from right to left. For the turn left signal, the left sided tail-lights flash in the sequence from left to right. There is a half a second pause between each step. Turning on both the L and R signals makes all eight lights flash on for half a second and off for half a second, corresponding to the emergency flash signal. When the L and R signals are off and the B signal is on all eight lights turn on to indicate braking. If the turn right R signal is on and the B signal is pressed then the right tail-lights follow the sequence and the left tail-lights are on to indicate ...

Need to design a FPGA based NMR Spectrometer for NMR Applications. Phase 1 : Interface high speed ADC and DAC with Altera FPGA and write the software for generating RF pulses and Capture Echo Signal from ADC. See the attached similar work for more details.

I would like someone to help me build a simple FPGA Kernel for a certain gaming system. I would like your help to improve a FPGA project we are using Altera Quartus programming software i have attached a QAR file First of all, compile it to a POF file and then send it to me and let me examine it and I will give you more instructions on how to proceed. It's not very complicated Let me ask you one question. What version of Altera Quartus did you use and how did you manage to compile it?

A catchy name for a system we will market to business that has a) video calling b) phone calling c) messaging - Has to a single word eg Zoom (but not Zoom!) - Not have "com" in there - Be less than 9 letters - Target businesses - Can Be adventurous- name does not need to actually have anything do with calling etc. Has to sound catchy eg Altera or something to that effect !

Montar 10 (dez) variações do anúncio. (Leia o item IMPORTANTE abaixo) são 10 modelos de imagens para publicidade no facebook com texto. IMPORTANTE: O Texto é Padrão, só altera o produto oferecido e a imagem do fundo. Para aprovação do projeto pode ser feito apenas 2 ou 3 modelos para eu ver como eles vão ficar, após a aprovação os 10 devem ser entregues para conclusão e liberação do pagamento. Preciso dos 10 arquivos editáveis de maneira que eu possa editar depois... Preciso dos 10 arquivos em PNG para eu publicar no facebook O Designer tem total autonomia para criar e desenvolver conforme sua ideia, caso queira uma dica, eu pensei numas imagens q...

I'm building a license plate detection system, and concept has been proven using MATLAB. The current challenge is to implement the design on an Altera DE Board FPGA using VHDL. At this point, because of time constraints I like to ask for ur assistance in the following areas I seek someone who could help Implement the design on an FPGA. Attached is the matlab code

Hello, i want to create project using altera DE2-115 board to detect edges on 3 image using sobel filter and show they ober VGA 640x480. To choose which image should be apear is needed 2 swtich. i have done some algorithm with matlab and now i have to implement it on altera. Thanks