VHDL Multiplexed DDS using iCE40UP5K board. Need post-synthesis Verification and debugging

I'm currently a 4th year degree student undergoing a project to build a Multiplexed DDS using iCE40UP5K breakout board. Apart from the Multiplexed DDS core itself, an i2s module for a DAC chip, Encoder modules for control of waveform parameters and an LCD module are present. Functional verification is done and behavior in simulation is as expected. What is needed is proper post-synthesis simulation (verification an debugging) so that I can deploy the project to the FPGA itself as no correct output is present, and am not experienced enough to do post-synthesis verification. Deadline is for 8th June 2018. I'd like to spend the least possible as I don't have a fixed income as a student. Thanks