FPGA implementation of face detection system using haar classifiers.

I have worked in the field of Real Time Image Processing before. You can check out my LinkedIn profile [login to view URL] I can also provide you with HDMI and Camera interfacing. Relevant Skills and Experience Have worked in Real time image processing on FPGA from functional to full Implementation on FPGA. I am also skilled in MATLAB which i use for verifying the functional design of the algorithm. Proposed Milestones ₹10000 INR - Matlab simulation and a functionally working prototype of the algorithm in verilog ₹10000 INR - After full timing analysis and a version implementable and working on FPGA ₹5000 INR - With the camera and HDMI interfacing

Hello dear, I have a lot of experience in Computer Vision applications / image and video processing in mobile and windows applications, My Team experience includes Port Based container Damage detection Software: detecting damaged container and keeping record and report of containers movement, Driver fatigue detection using raspberry pi which in a matter of milli seconds determines if the driver is sleeping or not and alarm accordingly using OpenCV, Vehicle counting in the particular category they belong to on a high speed road, number plate recognition using OCR algorithm of openCV, face detection and recognition for attendance system of a school and patient management system of a medical system. In short We have all the experience needed to complete the project with maximum accuracy. I will be waiting for your kind response. Regards

Completed many projects on FPGA based HW acceleration including acceleration of dense optical flow, QP solvers etc.., using both HLS and custom RTL design and implemented them to work on zynq soc. Relevant Skills and Experience Proficient in image processing algorithm development (implementing algorithms from scratch when accelerating ) , Using HLS tools for quick prototyping, writing custom Verilog RTL for tighter specs. Proposed Milestones ₹20000 INR - HLS implementation of the Viola Jones algorithm and optimization of design using HLS. ₹7777 INR - Implementation of IP on zed board to demonstrate the application. Which FPGA are you targeting ? (Zynq/Virtex)? What are your latency and throughput specs?

My team has implemented quite a few algorithms in FPGA (Spartan series), and this will be an easy task.