VHLD CODE STATE DIAGRAM

Dear sir, I am high skilled VHDL engineer with more than 63 VHDL projects on freelancer.com only, you will be more than happy with the work done, please check my profile for the VHDL work that i have done, i hope that i can have the chance to work with you. Best Regards;

Hi this is a simple state machine code and I can help you to solve the task. Let me help you on this !

hello , i can do this 1 day ........thanx ..... waiting for your reply.....regards ................//////////////////////////////////////////////////////////////////////////

Dear Sir, I saw your job ads and i'am confident that i have the required skills to do it . in fact i'am a telecom with extensive knowledge about mixed signal design and vlsi. moreover i worked with cadence virtuoso and enconter to design ASIC chip i'am looking forward to hear from you

Hi, I would be happy to help you, I have a master degree in electronics and computer science engineering. I've been programming in VHDL for many years. Message me so I can send you the solution. Cheers

Hi! Could you can refine the task. In code TYPE Statetype IS (A, B, C, D, E, F, G, H, I); so A-I are state of FSM. X1 -X10 are also the states of machine, because IF (DIN = '1') THEN state <= B; ELSE state <= X1; The X1 -X10 variables can be set to any values from A to I. Maybe X9 or X10 should be A if you want that FSM return to initial A state. If you need exactly mapping X1-X10 to A-I, then one VHDL-code is not enough

I'm an ASIC develop engineer, writing verilog/sysverilog codes everyday in my work. The codes you posted isn't long, not hard to explain the mechanics about it. Hope I could help you.

Hi I am an Electrical Engineer with more than 15 year experience in High speed FPGA designs. I'm proficient in Verilog and VHDL . Best Regards Ofer

Hello SalammR, The solution to your project is ready. I can also help you further with your other codes also. Thanks n regards rborax

Hi, I'm Verilog/VHDL expert and can surely help you. To know what condition variables X1-X10 should be, I need to know functional description of the VHDL entity. Could you please describe it?

it depend in what you need...; i can do it for you for free, but i need to know what you want from the VHDL code to do. Because depending on that you will choose the values of X1..X10 contact me, i need only a promotion from you, i do it even for free but this not permetted

I am having 10+ years of experience in the VHDL , I can give you the project in couple of hours itself. Thanks Shobhit K.

Hi! I have 7+ experience in writing vhdl for fpga! I was a digital design engineer at the university of Grenoble INP. I can help you! Please tell me what is your email address cause I finished your code and I want to send it to you. Please accept my offer, to begin our business!

A proposal has not yet been provided

i will complete this project as per requirement. i have experience in VHDL/verilog . You can settle our full remuneration after full completion of project.

Thanks for the project. I am Gopinath from India having vast experience in .Net field and programming. I have done my Master of Engineering in VLSI Design and obviously I know HDLs(both VHDL & Verilog HDL). I did lot of projects in front end(i.e,Coding part) using Xilinx(all latest versions) and also in designing Layouts & Schematic using back end tools(Tanner, Mentor Graphics, etc). You can see sample in my portfolio. As your project perfectly suits under my expertise, I am interested to work on this project. I can do this project at 11$. Sample work can be done so that you can understand my skills better. My Question: "For all the problems, the states and conditions may vary(i.e., for one, 'X1' might be 'A' & for another one, 'X1' might be 'B'). So if you let me know the exact problem for which we are working for, I can code for the conditions exactly." Looking forward to hear from you. Regards, Gopinath M

I will use Quartus and generate a MOORE state machine . The machine will be clock synchronised. If you want a MEALY state machine then i can design that as well. The state machine, VERILOG/VHDL code along with a test bench and waveform will be provided

It's a simple finite state machine example, I am an electronic engineer and well experienced with this kind of VHDL digital projects

Hello dear, I'm a French Verification Engineer working for STMicroelectronics. Don't hesitate to contact me if you need more information. Best regards, Mehdi