Enable dynamic clock tuning on Xilinx FPGA design

Dear sir I have more than 10 years experience in digital design using FPGA I can do the required design, please message me so that we can discuss

Hi I have been working on Verilog-VHDL and Xilinx and Altera FPGAs by more than 5 years. Please let me know if the requirement is still there I can work on it. The price mentioned is negotiable according to your requirements. Thanks

Hi there, I have read your project description and i'm confident i can do this project for you perfectly.I still have a few questions. please leave a message on my chat so we can discuss the budget and deadline of the project. Thanks . .

I can write the VHDL code for the FPGA that gets the clock rates as inputs thru sw pins and set the loops accordingly. I would do it with lower cost if it only needs to set the clocks w/o other functionalities. We may discuss it more in chat. Regards,

Hi. I'm FPGA based Embedded system Engineer. I have worked on dynamic clock synchronization. I can set the clocking values via switches or any other required peripheral. I can also sync your design according to the new clock. Please contact me and we can discuss further details. thanks

Hi Its possible to do this so that you can configure the clock from a pc. That way you can set any frequency you want within the range of the MMCM. Regards Jon

Hi! I'm interested in your project and I have a few questions: - What is the language of your project? (VHDL or Verilog?) I'm more comfortable with VHDL (I've done a similar task in my project in VHDL), but I'm also able to do it in verilog, if your project is done in verilog. - What is the original clock frequency and what is your desired frequency range? - What is the target operation system for the python-driven frequency setting? FYI: I do not have this board at home, so I can test it on another board, or provide the simulation result, together with the source codes and final bitstream. If there is something wrong after programming the board, I can debug it after your feedback. (But I think that well simulated design will work well in the HW for this project.)

A Data Scientist with experience in Python, R programming, R Shiny, R studio and anything related to data science and python Master in Engineering, Electrical and Electronic Engineer, who is dynamic, reliable, resourceful, committed and organized with enthusiastic approach to succeed with a pleasant attitude. Possessing excellent analytical skill and good research background. I have successfully completed IELTS with an overall band of 7 and have a good proficiency in English 10 Years Experience in Data Science Data Visualization Power BI Tableau Business development Anything on R programming COMPLETED PROJECTS • FM radio. • VHDL Design of an Up/Down Counter. • Design of Up/Down Counter using PIC. • Duck Shooter Program using C. • Pointer movement controller on 2-dimentional axis using C. • LCD display Manipulation projects including: o Text Display o Volt-Meter • Analog to Digital Conversion (8-bit). • Sound to Light Color Organ Design and Development. • Minesweeper Player Creation using PIC. • Simulation of an End to End Communication System with MATLAB. • (BENG Individual Project) (MENG Part A). • (MENG Individual Project) (MENG Part B). • (MENG Group Project).

I can do this I have specialization in following: Embedded System Design based on • Digital System Design (FPGA, CPLD) • Signal and Image Processing Algorithms • Micro-Controllers & Processors  Hands on experience on following platforms: 1) Xilinx heterogeneous architectures: ZYNQ 7020, 7035 and 7045 SOC FPGAs. 2) ZYNQ 702 and 706 FPGA boards. 3) Xilinx low power FPGAs Artix 7, Nexys 2,3 and 4 boards. 4) Xilinx low density Spartan FPGAs. Spartan 3E FPGA development kit. 5) Trenz TE0782 & TE0783 SOM FPGA boards. 6) Intel: Cyclone 10 FPGA development kit. 7) Analog devices: Realtime 3G/4G SDR based ADI RF integrated devices. 8) Atmel AVR microcontroller ATmega16/32/328, Arduino (Uno, Mega & Nano), (PIC based) chip kit.

Hello there, i have the ARtix-7 FPGA board with me and i have good expertise with VIVADO and VHDL/Verilog based design flow. I have worked on clock pre--scaling project many times. So i can do your project with dynamic clock configuration. Let me know your interest!

Wow, Wonderful! I met the first FPGA project in freelancer :) I am FPGA (VHDL) expert! so I can help you. I 'd like discuss with you via chatting. I will wait. Thank you! From Apollo!~

Hello, I have read the details provided and i am positive i can provide quality work,please contact me to discuss more on the project deadline and some other few things

Hi, I am having 28+ years of rich R&D experience in Embedded Hardware systems, FPGA based systems, Circuit design, Validation, Microprocessor/ Microcontroller based design Analog & Digital hardware design, Logic Design & Synthesis/Simulation, high speed board design, System design, Project management, Certifications & development for Consumer, Industrial and Defense products. I have worked 10+yrs in companies like Mentor Graphics and Defense systems. With my knowledge, I can virtually do any project within the given time frame. Waiting for your response

Hi, Are you using an MMCM or PLL to generate the clock? Either way, both primitives support dynamically changing the frequency by adjusting the Multiplier and Divider ranges of the primitive. What frequency range do you need to support? I would go by implementing a state machine that, when triggered by the sw pins, would reconfigure the clock and reset the design. Thanks, Tamas

Hi, I understand your requirements. I an a design engineer in xilinx Apps Team, I have worked on xilinx RFSOC Target reference design as well as VCU Target reference design for ZCU111 and ZCU106 Boards respectively. I a couple of solutionss for your problem. Simplest one could be to use a clock MUX with a reset mechanism. Another could be using a Clocking wizard with dynamic clock setting. Let's discuss it more, if you are willing to take it further. Thanks, Yashwant I have been working with xilinx FPGA, SOC, MPSOC and Versal since 2012 https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841711/Zynq+UltraScale+MPSoC+VCU+TRD I am the hardware developer for all of these designs