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$20 USD / heure
Drapeau de ESTONIA
tallinn, estonia
$20 USD / heure
Il est actuellement 8:58 AM ici
Rejoint le juin 12, 2020
0 Recommandations

Pavel M.

@botnursery

 5,0 (2 commentaires)
1,6
1,6
100%
100%
$20 USD / heure
Drapeau de ESTONIA
tallinn, estonia
$20 USD / heure
100 %
Travaux complétés
100 %
Suivant le budget
100 %
Dans les temps
N/A
Taux de réembauche

FinTech & FPGA design

fpga design, digital electronics, low-level programming, radio electronic devices and systems, financial and cryptographic applications
Freelancer Electronics Engineers Estonia
Voir tous les Electronics Engineers en Estonia

Contactez Pavel M. concernant votre travail

Connectez-vous pour discuter de tous les détails via la messagerie.

Portfolio

8689735
ZYNQ-7000 EBAZ4205 Minimum Board Operating Configuration EBAZ4205 is mining board used in Ebang Ebit E9+ bitcoin miner machine. This board features 256MB DDR3 memory, 128MB NAND Flash memory, 10/100MBit Ethernet and speed grade -1 Zynq 7010 ** New additions and changes in this fork: https://github.com/botnursery/EBAZ4205-Minimum-Board-Operating-Configuration
ZYNQ EBAZ4205 Base Configuration Design Project
ZYNQ-7000 EBAZ4205 Minimum Board Operating Configuration EBAZ4205 is mining board used in Ebang Ebit E9+ bitcoin miner machine. This board features 256MB DDR3 memory, 128MB NAND Flash memory, 10/100MBit Ethernet and speed grade -1 Zynq 7010 ** New additions and changes in this fork: https://github.com/botnursery/EBAZ4205-Minimum-Board-Operating-Configuration
ZYNQ EBAZ4205 Base Configuration Design Project
6641105
Datasheet on SHA256 hash checker IP (intellectual property virtual component) including verilog sourses https://github.com/botnursery/METRICSgit SHA256 hash checker can be used for massive hash reconciliation or in Bitcoin miners designs.
Datasheet on Verilog SHA256 hasher IP core
Datasheet on SHA256 hash checker IP (intellectual property virtual component) including verilog sourses https://github.com/botnursery/METRICSgit SHA256 hash checker can be used for massive hash reconciliation or in Bitcoin miners designs.
Datasheet on Verilog SHA256 hasher IP core
Datasheet on Verilog SHA256 hasher IP core
8681459
FSM (finit state machine) in Verilog to control the taillights of a 1965 Ford Thunderbird modeling
Finit State Machine to control Ford Thunderbir taillights
FSM (finit state machine) in Verilog to control the taillights of a 1965 Ford Thunderbird modeling
Finit State Machine to control Ford Thunderbir taillights
FSM (finit state machine) in Verilog to control the taillights of a 1965 Ford Thunderbird modeling
Finit State Machine to control Ford Thunderbir taillights
7212855
C++/ Quartus/ Cyclone IV/ RTL
NIOS II system with SDRAM mapped to VGA
C++/ Quartus/ Cyclone IV/ RTL
NIOS II system with SDRAM mapped to VGA
7431229
Low level coded (on asembler) module for AVR ATmega328P. ADC to pulse-position modulation (PPM) XY chanels encoder.
PPM (Pulse-position modulation) module
Low level coded (on asembler) module for AVR ATmega328P. ADC to pulse-position modulation (PPM) XY chanels encoder.
PPM (Pulse-position modulation) module
7129210
AES circuit and their testbench. Rijndael substitution box are implemented on forward s-box. The key length is 128 bits. https://github.com/botnursery/METRICSgit based on https://github.com/pnvamshi/Hardware-Implementation-of-AES-Verilog
Using the AES encryption module in Xilinx Vivado
AES circuit and their testbench. Rijndael substitution box are implemented on forward s-box. The key length is 128 bits. https://github.com/botnursery/METRICSgit based on https://github.com/pnvamshi/Hardware-Implementation-of-AES-Verilog
Using the AES encryption module in Xilinx Vivado
8689735
ZYNQ-7000 EBAZ4205 Minimum Board Operating Configuration EBAZ4205 is mining board used in Ebang Ebit E9+ bitcoin miner machine. This board features 256MB DDR3 memory, 128MB NAND Flash memory, 10/100MBit Ethernet and speed grade -1 Zynq 7010 ** New additions and changes in this fork: https://github.com/botnursery/EBAZ4205-Minimum-Board-Operating-Configuration
ZYNQ EBAZ4205 Base Configuration Design Project
ZYNQ-7000 EBAZ4205 Minimum Board Operating Configuration EBAZ4205 is mining board used in Ebang Ebit E9+ bitcoin miner machine. This board features 256MB DDR3 memory, 128MB NAND Flash memory, 10/100MBit Ethernet and speed grade -1 Zynq 7010 ** New additions and changes in this fork: https://github.com/botnursery/EBAZ4205-Minimum-Board-Operating-Configuration
ZYNQ EBAZ4205 Base Configuration Design Project
6641105
Datasheet on SHA256 hash checker IP (intellectual property virtual component) including verilog sourses https://github.com/botnursery/METRICSgit SHA256 hash checker can be used for massive hash reconciliation or in Bitcoin miners designs.
Datasheet on Verilog SHA256 hasher IP core
Datasheet on SHA256 hash checker IP (intellectual property virtual component) including verilog sourses https://github.com/botnursery/METRICSgit SHA256 hash checker can be used for massive hash reconciliation or in Bitcoin miners designs.
Datasheet on Verilog SHA256 hasher IP core
Datasheet on Verilog SHA256 hasher IP core
8681459
FSM (finit state machine) in Verilog to control the taillights of a 1965 Ford Thunderbird modeling
Finit State Machine to control Ford Thunderbir taillights
FSM (finit state machine) in Verilog to control the taillights of a 1965 Ford Thunderbird modeling
Finit State Machine to control Ford Thunderbir taillights
FSM (finit state machine) in Verilog to control the taillights of a 1965 Ford Thunderbird modeling
Finit State Machine to control Ford Thunderbir taillights
7212855
C++/ Quartus/ Cyclone IV/ RTL
NIOS II system with SDRAM mapped to VGA
C++/ Quartus/ Cyclone IV/ RTL
NIOS II system with SDRAM mapped to VGA
7431229
Low level coded (on asembler) module for AVR ATmega328P. ADC to pulse-position modulation (PPM) XY chanels encoder.
PPM (Pulse-position modulation) module
Low level coded (on asembler) module for AVR ATmega328P. ADC to pulse-position modulation (PPM) XY chanels encoder.
PPM (Pulse-position modulation) module
7129210
AES circuit and their testbench. Rijndael substitution box are implemented on forward s-box. The key length is 128 bits. https://github.com/botnursery/METRICSgit based on https://github.com/pnvamshi/Hardware-Implementation-of-AES-Verilog
Using the AES encryption module in Xilinx Vivado
AES circuit and their testbench. Rijndael substitution box are implemented on forward s-box. The key length is 128 bits. https://github.com/botnursery/METRICSgit based on https://github.com/pnvamshi/Hardware-Implementation-of-AES-Verilog
Using the AES encryption module in Xilinx Vivado

Commentaires

Modifications enregistrées
Montre1 - 2 sur 2 commentaires
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5,0
€30,00 EUR
Quartus Prime (FPGA Intel) Programming Expertise
Pavel was stellar. I have worked with a lot of excellent freelancers in my time but Pavel was constantly going above and beyond to deliver on the project. Without his help the project would have suffered, and instead, with the results he procured the project has really delivered. I cannot emphasize enough what an excellent help Pavel was. Timely, accurate, responsive, on-budget and ultimately more than eager to actually help!
Electronics
Verilog / VHDL
Microcontroller
Electrical Engineering
FPGA
L
Drapeau de Luis L.
@luislopez1994
•
il y a 3 ans
5,0
$30,00 USD
Find FPGA expert - pin assignment
Thanks Pavel. I will contact you again on next job
Electronics
Verilog / VHDL
Microcontroller
Electrical Engineering
FPGA
B
Closed User
@bwtxzj
•
il y a 4 ans

Expérience

Team Lead, Developer

METRICS Directions OU
nov. 2011 - Jusqu'à présent
Startup working group in development and implementation (FinTech). Development of hardware (FPGA) miner, adaptation of the SHA256 hashing for RTL layout in Verilog, analysis of time constraints and clock frequency, preparation of a testbenches. Design and development of DeFi smart contracts (Solidity). Deploying lightning network nodes (LND/LNbits), inspect and maintain functionality. Algorithm development and implementation.

Senior Specialist

IT departments Top10 Russian banks
déc. 2000 - mars 2008 (7 ans, 3 mois)
Participation, coordinator and developer in Project working groups in design, deployment and support of the corporate information system

Éducation

Magister

Vysšaja Škola Ekonomiki, Russian Federation 1994 - 1996
(2 ans)

Engineer of radio electronic devices and systems

Moskovskij Energeticeskij Institut (Tehniceskij Universitet), Russian Federation 1978 - 1984
(6 ans)

Qualifications

Specialization

University at Buffalo
2022
Blockchain Smart Contracts Decentralized Applications (Dapps) Blockchain Platforms

Certificate

Vanderbilt University
2020
MATLAB Programming for Engineers and Scientists

Certificate

Politecnico di Milano
2020
Developing FPGA-accelerated cloud applications with SDAccel

Publications

Specifications

GitHub
https://github.com/botnursery/METRICSgit

Contactez Pavel M. concernant votre travail

Connectez-vous pour discuter de tous les détails via la messagerie.

Vérifications

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Meilleures compétences

Electronics 2
Verilog / VHDL 2
Microcontroller 2
FPGA 2
Project Management

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