Band Pass Filter
par ahmedmohamed85
This project represents the design of an FIR Band Pass Filter, the filter code and the test bench were written in VHDL and the simulation shown was done using Modelsim
Me concernant
10 year's experience in digital system design using VHDL and verilog for FPGA's and CPLD's both for Xilinx and Altera Chips. I also have 10 years experience in working with Xilinx Ise form version 6.2 to 14.7 and Altera Quarus 2 for VHDL , verilog, system verilog and ip in addition to experience in Vivado design tool, and HLS and digital design using zynq7000
