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synopsis testing and verification of a Sdram ddr along with fpga verification
“It was really nice to work with Rajagopal. He completed project on time and in the budget. I would definitely love to recommend him to others because of his consistency and sincerity. He is brilliant and good human being too. Many many thanks to Rajagopal.”ravishaha il y a 5 jours
VHDL embedded systems project electrical engineering
“Very good at embedded systems and VHDL. All requirements and constraints of the project were met. Definitely recommended for your engineering projects. Will hire again!”RayM97 il y a 3 mois
Write an article about UVM (universal verification methodology)
“Good Understanding in verification methodologies.”ewizlab il y a 4 mois
Project 15791852 has been deleted
“Very good expert with excellent communication skills. Will hire again.”worldcitizen324 il y a 4 mois
Functional Verification of SHA-1 algorithim using UVM -- 2
“It was a great experience to work with Rajgopal S. He delivered the project on time”rohitgupta358 il y a 4 mois
implement one project with system verilog in Zynq
“I am for 200% recommend Rajagopal S. fo VHDL-Verilog and System Verilog. he is so much professional in every aspect. I am so glad of his Job and will continue to work with him in future.”Tomi1000 il y a 5 mois
Senior verification engineerJul 2016 - Nov 2017 (1 year)
Block level verification of ethernet switches.
Verification engineerJul 2013 - Jun 2016 (2 years)
Verification of ethernet switch(both custumer end switch, ISP switch) ,Central memory management controller using Systemverilog,UVM.
Asic Design/verification engineerJun 2011 - Jun 2013 (2 years)
Verification of ethernet switch ,scheduler,Txole, DMA (AXI) using System verilog UVM.
BE2007 - 2011 (4 years)
Diploma in ASIC (2011)RV -VLSI design centre
Whole flow of ASIC with hands on project(Design,DV,STA,PD,Layout).
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