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C Programming Data Processing Electronics Engineering Verilog / VHDL
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Muhammad A.

@MAsifBhatti

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Digital System Designer

$35 USD / Hour

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Pakistan (9:20 AM)

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Joined on May 28, 2008

$35 USD / Hour

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I have been working in design and development of digital systems. I have experience in designing with DSP processors, microcontrollers and FPGAs using Verilog HDL. My roll has been to design and translate it into schematics, writing bootloader, low level drivers and writing HDL for FPGAs used in system. My thesis topic in my doctorate has been the design of high throughput DSP architectures.

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Education

Beihang University

2016 - 2019

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3 years

PhD

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China

2016 - 2019

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3 years

Publications

An FPGA based 1.6 GHz cross-correlator for synthetic aperture interferometric radiometer

2017 Progress in Electromagnetics Research Symposium - Fall (PIERS - FALL)

This paper presents a 64-channel digital cross correlator capable of processing 1-bit digitized input data, sampled at the rate of up to 1.6 GHz thus enabling a high throughput imaging system. Using this correlator architecture, we were able to achieve a throughput of 1.6 GHz in Xilinx XCKU115 FPGA

Frequency Based Design Partitioning to Achieve Higher Throughput in Digital Cross Correlator

Sensors

In this paper we are presenting a high throughput digital cross correlator, capable of processing 1-bit digitized stream, at the rate of up to 2 GHz, simultaneously on 64 channels i.e., approximately 4 Trillion correlation and accumulation operations per second. In order to achieve higher throughput, we have focused on frequency based partitioning of our design and tried to minimize and localize high frequency operations. The design is implemented on Xilinx Kintex UltraScale device.

Coarsely Quantized Digital Correlators for Passive Millimeter Wave Imagers: A Hardware Perspective

2019 16th International Bhurban Conference on Applied Sciences and Technology (IBCAST - 2019)

This article presents correlators with three different quantization schemes having same number of channels and sampling frequency. All three correlators are implemented for the same device to highlight the difference in hardware utilization, making it a reference for any relevant work. The 64-channel correlators are implemented for 2-level, 3-level and 4-level quantized input data.

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