I Need a VLSI work to be done using verilog. It can be run using Xilinx ISE or Vivado
29 freelance ont fait une offre moyenne de 425 $ pour ce travail
I had done MS in Digital system design and VLSI design. Also I had 8+ years of experience in the field of FPGAs, Verilog HDL and VHDL. I am very familiar with Xilinx ISE software. I can do this task for you.
I'm working on Analog Mixed Signal project at a semiconductor company. And I have enough tools to perform your requests regarding Verilog. (Cadence Tool)
i did vlsi projects as part of my academics.i am good i digital design.if the task was described and given a chance to do that project i am happy to do that projects
Having worked on various industry projects in the past decade, I have the requisite exposure to complete the synthesis ready netlist. Please feel free to discuss more with more details.
Please email your specifications to my email address wiradesigner@ gmail.com. I have taped out several ASIC and SoC designs successfully through out my 16 years of experience.