VHDL expert needed

Design a serial communication protocol i.e., telegram containing data bus, address bus, read/write bus and checksum(CRC).

1. read/write access is to be transferred. If CPU is doing a write access, then it should have 1 byte address and 1 byte data and control bits if possible.

2. Read bus should read the address to be transferred.

3. The write bus should transfer the PSS signal or the chip select signal for the peripheral boards.

4. PSS is of 16 bits and the status of PSS signal should also be transferred.

5. The data should be on write access for front transfer and on read access for reverse transfer.

6. Define the type of telegram as read or write type.

7. Checksum should check if the data is valid or not.

Compétences : Verilog / VHDL, Electronique, Génie Électrique, Microcontrôleur, FPGA

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Nº du projet : #28995468