>>That is, convert input from serial to parallel, store data in RAM, take data from ram and send to

other data lines.

>>6-8 input detector-> counter value "4" puts data in to ram, then serial to paralel converter put in


>>d1 d2 d3 bytes to decode and then sepearte data from d1 d2 d3 to other data bus.

>>90 lenth, 90 width, is the frame size. LFSR is the data source.

1) COnvert shift register to incorportate frame detect ckt. (vhdl code)

hint: 16bit shift reg. start SR code. add decode vhdl code to detect frame:

F628 is the pattern of the code we're detecting.

Process; to be able to decode this circuit , we need a a testbench.

2) bit counter: 0-7: (Use frame detect)

3) byte counter: 0-809 (Use frame detect)

Please take a look and let me know what yu think.

Compétences : Verilog / VHDL

Concernant le client :
( 2 commentaires ) Mumbai, United States

Nº du projet : #1545517

2 freelances font une offre moyenne de 250 $ pour ce travail


Hi, I have 4.4 years of experience in VLSI domain including design, verification and FPGA bring up. Looking forward for your favor reply

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Nice to meet you, I am holding experience and knowledge in the digital design field. Kindly consider me to do this project.

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