Implementing a SimpleRisc processor with a 5stage pipeline in LogiSim

A LogiSim circuit of the SimpleRisc single cycle processor is provided.

This processor runs all SimpleRisc instructions and can execute any valid Sim-

pleRisc program to give correct outputs (provided the instructions are given in

binary/hexadecimal).

Compétences : Verilog / VHDL, Programmation C++, Programmation C, Génie Électrique, Microcontrôleur

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Nº du projet : #22012634