Hi, this project will require you to use verilog and basys3 board and logic analyzer to do the work. Contact me if you are an expert in this.
5 freelances font une offre moyenne de 50 $ pour ce travail
Hi, I am a senior digital design engineer, I have a broad knowledge of digital design in ASIC and FPGA using both VHDL and Verilog. I am using Vivado, ISE, and Quartise for FPGA, using DC, ICC, and prime-time for ASIC. Plus
Hi, I am Mtech graduate from IIT Roorkee and working on Hardware Description Languages Verilog and VHDL for the past 3 years. I have done many Digital system design projects using RTL design and FSM and had a working e Plus
i have five year of experience in FPGA using verilog/ SV, C/C++(HLS ARM) and python/TCL-TK. I have Basys3, zynq zedboad, nexex4 FPGA boad and i have developed many libraries and protocol on it. I have interface experna Plus