Design a block diagram for a smart watch using vivado.
6 freelances font une offre moyenne de 72 $ pour ce travail
Am a Mechatronic engineer with 5 year experience in my field and I believe i can handle your task to perfection.
Hi, I am a senior digital design engineer, I have a broad knowledge of digital design in ASIC and FPGA using both VHDL and Verilog. I am using Vivado, ISE, and Quartise for FPGA, using DC, ICC, and prime-time for ASIC. Plus
Hello, I hove gone through the job posting then understood the requirements and very much interested to work with you . I have five plus years of experience in verilog/vhdl. I have successfully finished multiple pr Plus
I am the best candidate for this Job because I am a computer Engineer with a Masters degree in Internet of things. I have done practice in Verilog/VHDL and well versed with microcontrollers. I also do PCB design hence Plus
Hi Client, I have experience in VLSI design and verification in many tools like xilinx, vivado, so i am sure i will help you, if you want more details you can freely contact to me. Thank you