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Design a block diagram for a smart watch using vivado.

6 freelances font une offre moyenne de 72 $ pour ce travail

(476 Commentaires)
8.0
BOSIREX

Am a Mechatronic engineer with 5 year experience in my field and I believe i can handle your task to perfection.

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 7 jours
(51 Commentaires)
5.5
moaazkh96

Hi, I am a senior digital design engineer, I have a broad knowledge of digital design in ASIC and FPGA using both VHDL and Verilog. I am using Vivado, ISE, and Quartise for FPGA, using DC, ICC, and prime-time for ASIC. Plus

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 10 jours
(30 Commentaires)
4.7
yakub6542

Hello, I hove gone through the job posting then understood the requirements and very much interested to work with you . I have five plus years of experience in verilog/vhdl. I have successfully finished multiple pr Plus

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 3 jours
(2 Commentaires)
2.7
snawoya

I am the best candidate for this Job because I am a computer Engineer with a Masters degree in Internet of things. I have done practice in Verilog/VHDL and well versed with microcontrollers. I also do PCB design hence Plus

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 6 jours
(0 Commentaires)
0.0
VLSIAkhi

Hi Client, I have experience in VLSI design and verification in many tools like xilinx, vivado, so i am sure i will help you, if you want more details you can freely contact to me. Thank you

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 7 jours
(0 Commentaires)
0.0