Job Description :-
We are a group building high performance configurable ASIC IPs that can fit inside a variety of products ranging from low power IoT ASICs to good performance Desktop/Server ASICs. The work centers around some of the advanced areas of chip design such as Cache Coherency, Virtual Channels and traffic performances, Pipelining for high-speed data and control logic, Clock-gating and Power-gating etc.
The work is in an advanced prototype stage and we plan to launch a product down the line. The team has people with chip-design experience in MNCs over decade and background of colleges as Indian Institute of Technology.
Job Requirements :-
1) We are looking for freshers or junior engineers who can code RTL and sub-unit Testbench from scratch with engineering supervision and broad level Microachitecture and Architecture Specs.
2) The person needs to have an excellent/good Verilog/SystemVerilog/Perl [login to view URL] coding will be Perl mixed Verilog/SV.
3) Knowledge of Make, Python, Bash is an advantage, but not mandatory.
4) The person needs to have a good understanding of the basic building blocks of an ASIC/FPGA design. Understanding of advanced concepts (as coherency) is an advantage, but not mandatory.
5) The person should have good energy to finish work in a timely manner, passion for RTL/TB coding, attention to details and humility to learn from right feedback.
Who can Apply :-
1) Fresher/junior engineers looking for an opportunity.
2) People looking for training/upscaling in the domain can apply.
3) People looking to explore in-depth from scratch ASIC design can also apply.
1) Opportunity to work in complex ASIC product design from scratch.
2) Opportunity to learn alongside experienced and passionate engineers.
3) Monthly Stipend/Remuneration.
4) Facility to work remotely.
How To Apply :-
Please apply answering below points -
1) Your expertise level in Perl, Verilog, System Verilog - Beginner/Intermediate/Expert.
2) Which area between design/verification you are more interested in.
Placeholder budget/timeline. Details to be discussed.
If you are sending a proposal, please be available in chat so that details can be discussed.
13 freelances font une offre moyenne de 25850 ₹ pour ce travail
Hello! Please check my reviews and profile to know more about me and my work. It would be great if I could help you out!
Hi, Hope you are doing good! I have more than 8 years of experience in ASIC design and verification. I have very good knowledge on verification using system verilog uvm. I have good hands on experience in verilog an Plus
Hello, I am a digital design freelancer and VHDL/Verilog expert with +5 years experience in RTL coding in both. I also have a good command in scripting in Tcl and Python. In addition, I have used some of Asic tools bef Plus
9 yr Experience in design &verification using vhdl verilog Sv UVM ovm . Will deliver on time quality work
Skills : Verilog, VHDL ,System Verilog , UVM, TCL, STA , Mutiple Clock Domain, Test bench verification , SoC system verilog verification , shell scripting , git Tools : Questasim, modelsim , Quartus , Xilinx ISE , Via Plus
hı i am an European freelancer having 5 years of experience on fpgas using VHDL and verilog. i didnot use perl or sv. i am core verilog designer with dsp background and various data interface knowledge such as ethernet Plus
Hi, I am very proficient in the Per, Verilog, System Verilog languages and have worked on many design and verification projects. I would be more interested in design projects. Please get back to discuss about the pro Plus
hi, I am a senior digital design engineer, I have a wide knowledge in digital design in ASIC and FPGA using both VHDL and Verilog. I am using Vivado, ISE and Quartise. 1) Peril >> Beginner Verilog >> Expert System Ve Plus
Dear Sir, I am Mtech graduate from Indian Institute of Technology (IIT) Roorkee and working on Hardware Description Languages Verilog and VHDL for the past 2 years. I have done many Digital system design projects usi Plus
I’ve a bachelor degree in electronics and communication, graduated this year with 93% grade. I’m highly interested in FPGAs and ASIC, I worked individually on some projects, and read books in the subject and took cour Plus
Hello, I am Sachin from Bangalore, have working experience on FPGA on Xilinx ISE & Vivado platforms using Verilog/VHDL. I have worked on applications of Image/Video/Speech Processing, Cryptography, Steganography, AES, Plus
I have took training in asic verification domain. 1) Your expertise level in Perl, Verilog, System Verilog - Beginner/Intermediate/Expert. : beginner 2) Which area between design/verification you are more interested i Plus
hi,my self rujal shah,i have completed my ASIC Verification training from semicon-tech.I can work on project at beginner level.