Verilog expert to design AXI PCIe IP in VIVADO

Fermé Publié le il y a 2 ans Paiement à la livraison
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AXI MM PCIe soft IP design in VIVADO with proper test bench and clear explanation on PCI BAR and AXI BAR. Interface simple custom AXI GPIO IP i have to control from host PCIe BAR Address.

Architecture Logicielle Bureau Windows Verilog / VHDL PCI Express

Nº du projet : #30214325

À propos du projet

4 propositions Projet à distance Actif il y a 2 ans

4 freelances font une offre moyenne de 11653 ₹ pour ce travail

IslamAdam998

Dear sir, I am a digital design engineer expert in FPGA and ASIC design flows using Verilog and VHDL programming. Also, I am experienced with Vivado, ISE, Vivado IPs, SDK, Quartus, Design Compiler, IC Compiler and ot Plus

₹7000 INR en 7 jours
(42 Commentaires)
6.1
moaazkh96

Hi, I am a senior digital design engineer, I have a broad knowledge of digital design in ASIC and FPGA using both VHDL and Verilog. I am using Vivado, ISE, and Quartise for FPGA, using DC, ICC, and prime-time for ASIC. Plus

₹6500 INR en 7 jours
(62 Commentaires)
5.4
satvikpatel9999

hello sir, currently I am working on PCIe window driver development and I have five year of experience on PCIe. I have working experience on xilinx zynq zedboard, nexus 3 and Cora board with Vivado and HSL too. I am pa Plus

₹11111 INR en 7 jours
(0 Commentaires)
0.0