AXI MM PCIe soft IP design in VIVADO with proper test bench and clear explanation on PCI BAR and AXI BAR. Interface simple custom AXI GPIO IP i have to control from host PCIe BAR Address.
5 freelances font une offre moyenne de 12322 ₹ pour ce travail
Hi, I am a senior digital design engineer, I have a broad knowledge of digital design in ASIC and FPGA using both VHDL and Verilog. I am using Vivado, ISE, and Quartise for FPGA, using DC, ICC, and prime-time for ASIC. Plus
Hi , i am working as FPGA Design Engineer. I have around three years of working experience in design and verification. I did my graduation back in 2017 and MS in 2019. I have follwoing skills: Skills : Verilog, VHDL Plus
Dear sir, I am a digital design engineer expert in FPGA and ASIC design flows using Verilog and VHDL programming. Also, I am experienced with Vivado, ISE, Vivado IPs, SDK, Quartus, Design Compiler, IC Compiler and ot Plus
hello sir, currently I am working on PCIe window driver development and I have five year of experience on PCIe. I have working experience on xilinx zynq zedboard, nexus 3 and Cora board with Vivado and HSL too. I am pa Plus