Fermé

ELECTRICAL ENGINEERING EE ELECTRONIC PROJECT CIRCUIT

Hi Bidders, the main thing in this bid is the time constraint. i need this project done within 24 hours time. Bidder must do this in 24 hours or earlier. All information is in the attachement. doen't needs to typed, can be hand written and scanned. Book used is Digital Intergrated Cicuit Design , Author : Ken Martin , ISBN : 0-19-512584-3, Oxford University Press There are total 4 problems.... Here's the perview... Problem 1 Design a 2-to-1 Multiplexor using Transmission-Gates (a pair of P- and N-channel transistors) and Inverter(s), by taking the following steps: a) Design the truth table, design and draw the circuit schematic diagram. b) Determine the size of transistors and state the criteria used in the determination. c) Derive VoutL and VoutH by calculating the voltage drops through the Transmission gates (assuming the technology process data outlined in Chapter 6 Section4, and with CL = [url removed, login to view]). d) Design the physical layout (polygon) patterns following the design rules described in Chapter 6 and in the lectures, and try to minimize the over all layout area. e) Draw a clean physical layout on a graph paper sheet using the following color map: Blue for metal layer, Black for contact, Red for Poly layer, Yellow for P - diffusion, and Green for N-diffusion. Label each signal terminal properly. f) Assemble answer sheets behind this page according to the above order. Problem 2 Design a positive edge-trigged (Master-Slave) D-type FlipFlop, with an asynchronous RESET, by taking the following steps. a) Design the truth table, design and draw the circuit schematic diagram and justify the chosen circuit type in one paragraph with no more then 50 words. b) Determine the size of transistors and state the criteria used in the determination. c) Calculate the rise-time and fall-time (assuming the technology process data outlined in Chapter 6 Section4, and with CL = [url removed, login to view]). d) Design the physical layout (polygon) patterns following the design rules described in Chapter 6 and in the lectures, and try to minimize the over all layout area. e) Draw a clean physical layout on a graph paper sheet using the following color map: Blue for metal layer, Black for contact, Red for Poly layer, Yellow for P - diffusion, and Green for N-diffusion. Label each signal terminal properly. f) Assemble answer sheets behind this page according to the above order. *************************************************** See All problems in Attachment

## Deliverables

1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done. 2) Installation package that will install the software (in ready-to-run condition) on the platform(s) specified in this bid request. 3) Complete ownership and distribution copyrights to all work purchased.

## Platform

Windows

Compétences : Ingénierie, MySQL, PHP, Architecture Logicielle, Tests de Logiciels, Administration Système, Hébergement Web, Administration de Site Web, Tests de Sites Web

en voir plus : the engineering design process, red black data, problem graph, php design patterns, paper package design, package label design, oxford university press, need electrical engineering, label and package design, i need a electrical engineering, graph problem, graph edge, graph data type, engineering needs, engineering design process, electronic technology, electronic electrical engineering, electronic and electrical engineering, electrical & electronic engineering, electrical design work

Concernant l'employeur :
( 8 commentaires ) Yonkers, United States

Nº du projet : #2952892

1 freelance fait une offre moyenne de $68 pour ce travail

hitechhuman

See private message.

%bids___i_sum_sub_32% %project_currencyDetails_sign_sub_33% USD en 1 jour
(3 Commentaires)
0.0