Optimize Exanic Card Latency

I am working with an Exablaze Exanic card in an OLTP environment and I am seeing end-to-end send latency hovering around 2–3 ms with the function encapsulating all the below functions costing about 1 us. All traffic is generated through the exasock API, with calls in roughly this order: exasock_tcp_build_header → exasock_tcp_set_length → exasock_tcp_calc_checksum → exanic_transmit_frame → exasock_tcp_send_advance My sole objective is to drive that latency down as far as the hardware allows. If you have hands-on experience squeezing microseconds out of Exanic-based pipelines—whether through driver parameters, FPGA firmware tweaks, user-space memory mapping, or smarter batching in the exasock code path—I would like your help. What I can provide • Source snippets and current build flags • Access to a staging server equipped with the same NIC and an OLTP test harness • Benchmarks collected with hardware time-stamps for every stage above What I need in return • A tuned configuration or code patch set that demonstrably lowers latency (before/after numbers captured with the card’s on-board clock) • A short write-up of the adjustments so I can reproduce the result in production If you have a proven track record lowering packet-send latency on Exanic or similar FPGA-accelerated NICs, let’s talk.

Project ID: 40580928