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Single Core and Pipeline MIPS Verilog

-Tools:Altera Quartus,Modelsim and FPGA.

-This Project is divided to two parts:-

[login to view URL] and implement a 32 bit architecture pipelined CPU with a single bus for a MIPS computer.

Found in figure 1 is a top level view of a single core single bus MIPS CPU. Use Quartus to design the

list of components found below in Verilog HDL.

1- Register File (16x 32)

2- ALU

3- Instruction Register

4- Control Unit

5- PC register

6- Shift logic unit

7- Conditional logic unit

8- Three-level Cache for the Data Memory (reading and writing)

9- Data Memory

10- Branch target address adder

In a 32 bit architecture CPU, for an opcode of 6 bits wide there should be 64 instructions. You are

required to function the following 10 instructions from the 64.

1- add

2- sub

3- load

4- store

5- and

6- or

7- branch if zero

8- branch if equal

9- branch if positive

10- branch if not equal

Make sure to design an adder that calculates the branch target address for all branch instructions.

Each component must be verified in software using a functional waveform. The fully connected CPU

should be also verified using a functional waveform.

[login to view URL] a pipelined architecture for this CPU with five stages (instruction fetch, instruction

decode, Execution, Memory, Write Back). Refer to Figure 2.

-This Project must be implemented on FPGA, u have to adjust the pin assignment to work on DE2-115 FPGA.

-All steps must be Full documented in word file and Clearly explained in English by video.

Compétences : Assembly, Ingénierie, FPGA, Microcontrôleur, Verilog / VHDL

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Concernant l'employeur :
( 1 commentaire ) Giza, Egypt

Nº du projet : #18791028

6 freelance font une offre moyenne de $317 pour ce travail

ahmedmohamed85

Dear sir I have more than 10 years experience in digital design using verilog please check my profile also please message me so that we can discuss

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7.8
ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a Plus

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6.1
raulbehl

Hello! Please check my profile and reviews to know a bit about me and my work. It would be great if I could help you out.

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6.0
taoyanglee

Greeting. I have rich embedded development experiences. I am very interesting in your project. I really hope to work with you. I'm working on quartus 13.0 and i'd like to discuss it in more details. Best regards.

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waqay002

Hi I have experience in HDL design and I am using vivado to implement these sort of projects. Let me know if you are ok with it. Thanks

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sharmavishal2201

I have Good Knowledge of RTL simulation(VHDL/ Verilog). I have experience 1+year in the VLSI Design Engineer with Lenronic Infotech Solution (P) Ltd. • Working on programming of VHDL and Verilog . Writing and perform Plus

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