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Sequential_ VHDL 1.

The counter will have three inputs: CLOCK, RESET, and ENABLE. The counter will output the count in binary. It will also have an ENABLE_OUT output.

The ENABLE input is to be active-low (the counter will be enabled if ENABLE = 0 and RESET =1) and the counter is rising-edge triggered. If ENABLE = 0 and RESET =1, the counter will count down by 1 on the rising-edge of the CLOCK (unless the count is at 1base10 and then the output of the count will go to 20base10 on the next rising edge of the clock). If ENABLE = 1 and RESET =1, the count will not change.

2. The RESET input is to be asynchronous (acts immediately and doesn't wait for the clock) and active-low (the counter resets when RESET=0). If RESET = 0, the count will be 2

Compétences : Electronique, Logiciels Embarqués, Ingénierie, Microcontrôleur, Verilog / VHDL

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