I need some help on a Altera FPGA testcase.
A 16bit bidirectional parallel data interface on FPGA's pins to write/read to/from a 48bit word FIFO.
Written in Quartus 18.1 with Verilog/System Verilog.
And a testbench for verification.
The FPGA pins used are a 16bit bi-directional data bus, a pin for write enable to bus (active low), a pin for read enable from data bus (active low) a chip enable (active low) for the data bus to be enabled for read/write and a pin that indicates FIFO has reached its 3/4 capacity.
Inside the FPGA will be a single FIFO with 1024 words that data will be written to it via the 16bit bus and read again via the 16bit bus. FIFO will have 48bits word length.
What is required is the complete Quartus project with source rtl files and a testbech to verify the proper behaviour of the design.
having more than 8 years of experience in the field of verilog and systemverilog verification. I can do this well without any functional issues.
5 freelance font une offre moyenne de $200 pour ce travail
Dear sir I have more than 10 years experience in digital design using FPGA, please message me so that we can discuss Best regards
Dear Sir. How do you do? I have seen your description very carefully and posting to you my idea. If you give me a chance to interview, I'll explain in more detail and I'll do my best for you. I will work hard and ha Plus
Hi I have read your description i want to discuss you the further details about the [login to view URL] you send me the code which is written so i can further assist you. looking forward to you regards Abdullah javaid
I am a telecommunication engineer. I have a grade A of FPGA IEEE course. I have had several FPGA projects before including more complicated staffs like OFDM and Wireless connections. Feel free to send me the details of Plus