System Verilog Expert (Electronics, Electrical ASIC)


I need system verilog expert who understand concept of verification, assertions and other basic concepts..


- Logic Design and Verification

- Verilog

- System Verilog

- Assertions

- TCL/Perl or scripting

- C/C++ programming is a plus

You should have access to necessary tools like mentor graphic or anything else.

More project details will be given to candidate with proper bid and message. Please let me know about your work experience / Projects you have done.

This might be 6-10 months project with about $500/month or more depending on how many hours you put..

But first I will test selected bidder and give them little verilog code/small project to work on to test you knowledge. So please bid only for test project you will be working on. For whole project, I might create new contract. Test project/code I give you will include testing you skills on verilog, system verilog and more...If you are know verification, you have big advantage...

I think test I take will not take more than 10 hours to an expert...You will be given 3-4 weeks to complete you test..just have to spend 2-3 hours a week..I will also see your time arrangement and how you approach deadline and all stuff....As this test will take 10 hours and I might ask 3-4 of you to take it, I dont be paying that much for test..bidding should be between $50-$100..

Once I see responses and your test projects, I will choose one of you and you will be paid around $500 a month for working hardly 30 hours per month..

Compétences : Génie Électrique, Electronique, Verilog / VHDL

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Concernant l'employeur :
( 10 commentaires ) Santa Clara, United States

Nº du projet : #4183685

Décerné à:


Hi, DV Expert here, with ~15 yrs of experience. I can do this for you. HIGH QUALITY guaranteed. More info on PM

%selectedBids___i_sum_sub_7% %project_currencyDetails_sign_sub_8% USD en 5 jours
(2 Commentaires)

9 freelance font une offre moyenne de $144 pour ce travail


Dear sir, I have more than 5 years experiance in HDL design and verification using VHDL verilog and system verilog

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 30 jours
(21 Commentaires)

Hi, I am MSc in VLSI design and have vast experience in this field. I can help you with this project.

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 3 jours
(9 Commentaires)

Hi,I can help u.

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 7 jours
(3 Commentaires)

I would like to have that challenge/project. I'm a 2ªyear electrical engineering student.

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 30 jours
(0 Commentaires)

Hi, Please see the PMB

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 30 jours
(0 Commentaires)

please check private message.

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 30 jours
(0 Commentaires)

I have a good working experience in Verification using system verilog, Comprehensive knowledge of the methodologies for implementing System Verilog Assertions to measure Functional Coverage and protocol checker.

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 30 jours
(0 Commentaires)

sir, i am working as a system engineer..i have good experience in system verilog, logic design and verification. i am also good in c and c++ programming.

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 2 jours
(0 Commentaires)