We need a Verilog/VHDL developer to write some simple blocks for the Virtex-7 FPGA. The development environment is Xilinx Vivado.
There are 5 blocks in total with the following functionalities:
1. CM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and testbench.
2. RDM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and testbench.
3. Clock-gen: Configure Xilinx PLL to generate the system clock and some divided clocks. Write testbench.
4. Latch block: Write a simple latch logic to control some outputs and testbench.
5. UART: Run verification on our IP with an existing testbench.
More information available for suitable candidates upon request
Dear sir I have more than 10 years experience in digital design using Xilinx FPGA, i can do all the required 5 Tasks perfectly, please message me so that we can discuss Best regards
12 freelance font une offre moyenne de €444 pour ce travail
Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a Plus
Hi I am very interested in your job as an experienced Hardware and firmware developer. For 7 years, I have been working in this field. I have very good experience with hardware design and firmware develop so can c Plus
A Data Scientist with experience in Python, R programming, R Shiny, R studio and anything related to data science and python Master in Engineering, Electrical and Electronic Engineer, who is dynamic, reliable, resou Plus
Hi! I have successfully finished a lot of FPGA projects, one of them found here, on Freelancer.com, you may find my employer feedback. Please contact me via chat to discuss implementation details of your requirements.
Hello I have over 10 years experience using Xilinx devices and working with Vivado. I would be happy to supply some example code that I have produced if that would be of interest. Thanks Jon
I've more than four years of industrial experience in FPGA, ASIC Design using VHDL, Verilog/Systemverilog. I've done multiple projects on Communication protocols and high speed signal processing. I've used multiple RAM Plus
I have 10 years of experience in design and verification using Verilog. This task is quite simple with me. Please message me. Best regards.
I am an European freelancer having 5 6 years of experience on fpgas using VHDL and verilog. I designed many Signal processing and communications systems in the industry and also here I have some big projects as you can Plus
I am experienced fpga ip core developer with a lot of experience on building ip cores. I have experience of working on development of verilog wrappers and testing of uart for virtex7.
I am working on Xilinx FPGAs for 3 yrs from now. Zynq and UltraScale+. Get the smallest block of problem. I will provide the solution. If you liked my way of working. We will go further.
Hi Sir, I have five years of experience in FPGA design. And I have strong skill in Verilog/VHDL coding. I have certification of Xilinx about design methodological. Below are some of the skill that I worked before: Plus