# Multisim project work

Can send you PDF if needed with pics

Design Project Information Sheet

1. Design Requirements

A translation table has 60 distinctive positions with the left most (position N = 1) and the right most (position N = 60). The functional block diagram for the electronic system that monitors and displays the table current position is presented in Figure 1.

Gk...G0

Gray code to Binary code converter

Memory (Previous position)

Move <Right or Left>?

LR Direction indicator

Bk...B0

BCD to 7 segment decoder

BCD to 7 segment decoder

Left Right Central

Alarm

Unit digit Ten digit

Current Position Indicator

Table current Position (N)

Reset (N =30)

The translation table provides the digital system of Figure 1 with a k-bit Gray code that indicates the table current position. The digital system of Table 1 consists of several functional blocks. The first block is the Gray code to binary code converter. This block takes a k-bit long Gray code and converts it to the equivalent binary code. The next block is the binary to BDC converter which converts the binary code to the BCD code to display the current table position on the 7-segment LEDs. There are several combinational logics that indicate the current table position of the table relative to left, right and center of the system. An alarm is sounded when the table position is at the extremity of the left and right positions. In addition, the system also has ability to reset the table position to the center (position N = 30) and to determine the table current movement (to the left or to the right).

The task is to design the system of Table 1 in Multisim, assuming the inputs to such a system are a k-bit long Gray code and the reset input; also assuming that the system operates in an asynchronous fashion. Details of the design task are explained in the next section.

Binary to BCD

1 ≤ N < 20 ?

40 < N ≤ 60 ?

on/off on/off

20 ≤ N < 40 ?

on/off

N <5 or N >55

on/off

Figure 1: Functional Block Diagram for the translation table position monitoring system

ENEE13020 © Dr Lam Bui 2018 2/4

1. This design must be based on discrete logic circuits.

2. No microcontroller is allowed.

3. Hierarchy design approach must be used. That is the functional blocks of

Figure 1 should be implemented using Mutism hierarchical blocks and integrated together to provide the system functionality as described in Section 1.

4. The design must be based on the smallest possible value of k that satisfies the system requirements of Section 1.

5. To achieve full mark, a full step by step derivation of your design solution must be provided with all justifications of choices and assumptions (see Section 3).

3. Reporting and Assessment Criteria

The design report must be prepared using the provided report template. It will be assessed against the following criteria

1) Determination of the value k.

2) Descriptions of the functionality and operation of each blocks of Figure 1

3) Derivations of the logic expressions for each blocks of Figure 1

4) Multisim schematics of the logic circuits for each blocks of Figure 1

5) Practical implementation of each blocks of Figure 1 (replacing the logic gates

and components by using suitable practical ICs)

6) Screen captures of simulations of each blocks to demonstrate their correct

operations.

7) The overall schematic of the entire system (integrating all the blocks together

as shown in Figure 1)

8) Practical implementation schematic of the entire system

9) Screen captures of simulations of the entire system showing its correct

operations as described in Section 1

10) Discussions on any unexpected or interesting finding during this design

project.

ENEE13020 © Dr Lam Bui 2018 3/4

4. Marking Information

Details of the mark breakdown are provided in the design report template. The mark allocation per assessment criteria as outlined in Section 3 are provided in the following table. There are a total of 100 marks and this assignment contributes 40% to the final mark of this Unit. You MUST pass this assessment in order to pass this Unit.

Description \ Criteria*

2

3

4

5

6

Total mark

Determination of k value

2

Gray to binary converter

2

4

2

4

3

15

Binary to BCD converter

1

3

1

2

3

10

Current position display

1

1

1

1

1

5

Relative position indicators

2

2

2

2

2

10

Memory Unit

1

1

1

1

1

5

Direction indicator

2

4

2

4

3

15

Entire system

8

8

9

25

Reset capability

5

Discussions and reflections

4

Technical presentation**

2

Professional presentation***

2

Total Mark

100

*Criteria are numbered as per Section 3

**Technical rigorous and completeness of the report such as back-up evidences, references, consistency of data, etc.

***Presentation such as formatting, references, quality of illustrations, etc.

5. Submission Guideline

• A complete submission must contain only two files. A single pdf report contains all references and supporting information included as appendices and a zipped file contains all relevant Multisim simulation files.

• At minimum, the Multisim implementations of the functional blocks of Figure 1 must be accompanied the design report. No Multisim file submission will automatically result in an ungraded ZERO mark for this assessment.

• All Multisim files must be copied into a single directory and each should be able to run independently from this directory without the need to access files from another directory.

• All Multisim files must be zipped into a single compressed file (.zip file).

• Please ensure that the Multisim files are runnable when unzipped as they will be

tested during marking to check for correct operations. Non-executable file is

equivalent to no file.

• The project must be submitted by the due date unless an extension is granted for

exceptional circumstances.

• Only requests for extension received by the Unit Coordinator (Dr. Lam Bui) for at

least 72 hours prior to the submission deadline using a formal application process will be considered.

ENEE13020 © Dr Lam Bui 2018 4/4

Compétences : Génie Électrique

Concernant l'employeur :
( 0 commentaires ) Australia

Nº du projet : #16719850

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