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FPGA QAR Project

13 freelance font une offre moyenne de ¥51965 pour ce travail

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% JPY en 10 jours
(368 Commentaires)
7.7
binyameen441

Hi There I have checked your project description and understand everything. I am very confident that i can do this project perfectly. Thanks

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% JPY en 10 jours
(35 Commentaires)
4.9
%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% JPY en 15 jours
(2 Commentaires)
4.1
andreird129

Hello How do you do? I am FPGA expert. I have strong team. I am expert about this field. I will help you. I think i can do it. I want to discuss about your project. I will do my best for your project.

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% JPY en 10 jours
(3 Commentaires)
3.9
%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% JPY en 10 jours
(14 Commentaires)
4.1
lokawiz

Hi, We would like to understand your project requirement better. We have good RTL and FPGA engineers who may be able to solve the issue with your QAR file compilation. Please review our RTL Hardware IP page at h Plus

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% JPY en 10 jours
(8 Commentaires)
3.7
olegkaravaev84

I have more then 10 years of an experience in the FPGA design and mostly with Altera FPGA. I think I can help You. But at first I need to see your project.

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% JPY en 7 jours
(3 Commentaires)
3.6
ReconLogic

I have in-depth knowledge of altera FPGAs and design software. I can help in figuring out the problem and fixing it.

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% JPY en 10 jours
(3 Commentaires)
2.9
sumbali

I have completed my MS in Electrical Engineering and working in the field of designing for last 3 years. My projects have won more then 10 national level competitions. Area of Expertise -Discrete Time Signal Processing Plus

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% JPY en 10 jours
(0 Commentaires)
0.0
%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% JPY en 10 jours
(1 Évaluation)
0.0
finicky1036

Hi Sir,, i can convert the file for you in most reasonable price.. for more details you can come inbox with me . you will be pleased working with me. looking forward at you. Best Regards

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% JPY en 7 jours
(0 Commentaires)
0.0
NienYi07

Hardware developer with extensive verilog development experiences in RTL coding, mapping and place and route in generating a bit stream. Strong in debugging and in getting image to work.

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% JPY en 10 jours
(0 Commentaires)
0.0
anilch3560

Hi I have 15+ years of experience in FPGA design & validation. I have worked with many Japanese customers like canon, Kyocera, Ikegami etc. I have worked on both altera & xilinx FPGAs. Relevant Skills and Experience Plus

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% JPY en 10 jours
(0 Commentaires)
0.0