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Error Correction Blocks Configuration (Viterbi+Reed Solomon) on an ARTIX7-200T FPGA supporting 200 Mbps is needed.

Error Correction Blocks Configuration (Viterbi+Reed Solomon) on an ARTIX7-200T FPGA supporting 200 Mbps is needed.

The bidder must use open source or free Viterbi decoders-Reed Solomon en/decoders-(De)Interleavers-Pseudorandom number generators (PRBS).

The Viterbi Decoder must be parameterizable (K=7, 1/2,3/4,7/8 puncturing etc.) and must support soft decision.

The Reed Solomon En/Decoder must be set to (223,255)

The Interleaver must be parameterizable

A Framer/Deframer must add/ remove Headers into the bitstream and should indicate a lock.

The Transmit Chain:

Data Source(PRBS)-> RS Encoder->Framer->Convolutional Coder-

The Receive Chain:

Viterbi decoder(soft decoding)->Deframer and Lock detection->RS decoding->PRBS Lock detection and BER Measurement

200 Mbps sustained decoding speed should me maintained.

Complete Simulation and HDL sources must be delivered.

The use of relevant Xilinx Evaluation cores are permitted.
All parameters should be set by registers.
It is a typical implementation of the standart TM SYNCHRONIZATION AND CHANNEL CODING which is located at https://public.ccsds.org/Pubs/131x0b2ec1s.pdf The relevant sections are: Section 3,4,5,8,9 which deal with the Viterbi decoder, RS encoder/decoder, framing and scrambling and it is much more restricted as we gave the specific parameters for the Viterbi and RS decoder. The implementation is sometimes referred as NASA CCSDS.
A simple noise generator (or AWGN) can be added just for test purposes, the Input output can be 4-8 bits.

Compétences : Génie Électrique, Electronique, Microcontrôleur, Ingénierie des Télécommunications, Verilog / VHDL

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Concernant l'employeur :
( 1 commentaire ) ANKARA, Turkey

Nº du projet : #16491276

7 freelance font une offre moyenne de $742 pour ce travail


A proposal has not yet been provided

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 3 jours
(419 Commentaires)

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I a Plus

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 10 jours
(89 Commentaires)

Hello, My name is Mohamed. I have 5 years experience in digital design and FPGA. I checked your project description about implementing Reed Solomon Viterbi decoder on an ARTIX7-200T FPGA which support 200 Mbps. I ha Plus

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 10 jours
(71 Commentaires)

I have extensive knowledge in digital design and Xilinx FPGAs, I hope working together, please contact over chat.

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 20 jours
(5 Commentaires)

Hi, We will configure your Error correction Block (Viterbi+Reed Solomon) on ARTIX7-200T FPGA. Base on your description it appears that you are looking to build a receiver system similar to that for 802.11n/ac WiFi o Plus

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 10 jours
(8 Commentaires)

Hello I have experience in FPGA communication projects. Bidding as per invite sent Happy to discuss and proceed. Thanks VJ

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 20 jours
(2 Commentaires)

Hi, this task is much difficult to the former one (BPSK ,QPSK...) . here again, i give some vital modules, and its main function. Module: Branch Metrics,Add-Compare-Select, register exchange, Traceback . Brief Descri Plus

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% USD en 10 jours
(1 Évaluation)