I have a digital input measurement signal, 0 ~ 1.1V level. Each pulse is an event, that has a level HIGH width from 5ns to 10ns, and the minimum time between every 2 pulses' rising edges is 20ns.
I need a system to histogram the time between all adjacent pulses' rising edges, that each bin of the histogram is 1ns wide. For example, starting from t=0, if the input signal has rising edges at t=3.2ns, 28.5ns, 528.6ns and 1528.7ns. Then in the histogram, Bin #25, Bin #500 and Bin #1000 have 1 respectively, and all other bins have 0s.
Bin Size: <=1ns
# of Bins: Up to 10K
What I need from you:
1. A plan on what I need to buy to build this system. I have a ZCU102 board. So maybe something like AD9234-LF1000EBZ? Do let me know your plan in your proposal.
2. The deliverable is the firmware, including ZCU102 PL side RTL and bit file, Petalinux Image and drivers.
3. Remote support, to set up the whole system.
4. A block diagram and a brief explanation about your RTL code.
Verilog is preferred.
Please in the proposal, let me know how long would the project take and how much would you ask to build it.
4 freelance font une offre moyenne de $1138 pour ce travail
Hello. After reading over your project this looks like a perfect fit for my skill sets. I looked at your proposal. I think that the main principle to measure the time interval between pulse rising edges is TDC. I h Plus
Dear Hiring Manager, I am interested in designing Histogrammer of 1ns Bin Size as per your requirement. I have 7+ years of experience in the field of Electrical Engineering. AD9234-LF1000EBZ-ND, 12 bit ADC, is okay Plus
I think that the pulse delay measurement can be done without any external components. If your information about the pulses input level (0V - 1.1V) is correct, then LVCMOS12 (1.2V IO standard) could work with this. If Plus
hi, i'm electronic engineer with work experiences as hadware engineer i had experience in designing systems using VHDL/verilog langage with xlinx and quartus envirenment i develop your program and assit y Plus