Fermé

adc ltc2308 in vhdl altera deo nano soc cyclone 5 board

It is a basic project but since I've never worked with on FPGA before, I think someone with experience is a wise choice. The project is basically read the ADC signal from onboard adc ltc2308 and send it to the DAC. While ADC (ltc2308 ) is 12bit

Compétences : Design de circuits, Génie Électrique, Electronique, Microcontrôleur, Verilog / VHDL

en voir plus : de0 nano pin assignment, de0 nano soc pinout, de0 nano pinout, de0-nano-soc projects, de0 nano soc manual, de0 nano manual, de0-nano-soc tutorial, de0 nano pin assignment file, adc spi vhdl, adc code vhdl spartan, vhdl altera servo, vhdl altera audio recorder, quartus vhdl fpga spi, fpga spi vhdl, fpga spi interface vhdl

Concernant l'employeur :
( 0 commentaires ) Germany

Nº du projet : #16279900

7 freelance font une offre moyenne de €65 pour ce travail

mastor31

Dear Sir/Madam, I am very good in VHDL and verilog coding with Xilinx Vivadi, ISE, Altera/Intel Quartus, Lattice Diamond. I worked with ADC/DAC devices of both serial and parallel interfaces. I believe that I am the Plus

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% EUR en 4 jours
(10 Commentaires)
4.1
%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% EUR en 10 jours
(5 Commentaires)
3.8
olegkaravaev84

I have more then 10 year of an experience in the FPGA/ASIC design, and the good skills in the both VHDL and Verilog.I think, I can help You.

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% EUR en 4 jours
(3 Commentaires)
3.6
okjang127

Hello! I have finished pattern recognition in DE-2 70 right now. Your Project very easy than above one. I have many experiences in vhdl and verilog . Please hire me. thank you.

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% EUR en 10 jours
(1 Évaluation)
1.1
abehin98en1992

I will be your better choice to help you finish this task, as I have lot of experience with design and testing of ADC and DAC data control schemes in FPGA.

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% EUR en 5 jours
(0 Commentaires)
0.0
NienYi07

Extensive knowledge in FPGAs with RTL coding, running simulations and debugging. Guaranteed to delivery on time and a high quality project.

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% EUR en 6 jours
(0 Commentaires)
0.0
%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% EUR en 5 jours
(0 Commentaires)
0.0