SystemVerilog RISC-V FPGA Implementation

@ducdctoandh

Hi! I can take this on. I have extensive experience with RISC-V datapaths and simulation bring-up (Vivado simulation flow, waveforms/debug, and ISA-accurate immediate/branch/jump handling). For your Experiment 4, I’ll fully re-implement IMMED_GEN and BRANCH_ADDR_GEN from scratch, strictly following the RISC-V encoding rules: Correct extraction for I/S/B/U/J immediates from instr[31:7] Proper sign-extension for each format Correct bit placement (especially B-type and J-type) Proper alignment/left-shifting (B/J include an implied low bit = 0) Correct target address computation for JAL / JALR / conditional branches JALR alignment masking (& ~1) per spec Deliver synthesizable RTL + clean waveform-verified outputs If you share the assignment PDF + your testbench + any expected immediates/waveform reference, I’ll match the expected sim outputs and annotate the logic so it’s easy to defend to your instructor.

@hayteekeys

Hi, KINDLY READ THROUGH MY PROPOSAL THIS IS WHAT I WILL DO - Re-implement IMMED_GEN in synthesizable SystemVerilog: extract & sign-extend I/S/B/U/J immediates from instr[31:7] per RISC-V spec (e.g., B-type: instr[31], [7], [30:25], [11:8], <<1, sign-ext). - Re-implement BRANCH_ADDR_GEN: compute JAL/JALR/branch targets (PC + imm, JALR rd1 + imm & ~1) with alignment, no overflow assumptions. - Verify in Vivado sim using your testbench – match expected waveforms & immediates, fix sign/bit errors. - Deliver: full SV sources, updated project files, waveform screenshots, short verification report. RELEVANT PROJECTS - 2025: RISC-V datapath modules (imm gen, branch calc) in Vivado SV for uni lab – fixed B-type sign-ext bugs, 100% waveform match. - 2024: Custom RISC-V CPU sim (incl. all imm formats) – per ISA v2.2, deployed in FPGA proto. QUESTIONS - Can you share assignment instructions, testbench, expected immediates, & reference waveform? - Exact RISC-V subset (RV32I only, or extensions)? - Target Vivado version? RISC-V RTL expert (daily Vivado SV). Ready to deliver correct modules in 3–5 days.

@hayat38402

Hi, how are you doing? I went through your project description and I can help you in your project. your project requirements perfectly match my expertise. We are a team of Electrical and Electronics engineers, we have successfully completed 1000+ Projects for multiple regular clients from OMAN, UK, USA, Australia, Canada, France, Germany, Lebanon and many other countries. We are providing our services in following areas:  Embedded C Programming.  VHDL/Verilog, Quartus/Vivado, LABView/ Multisim/PSPICE/VLSI  MATLAB/SIMULINK  Network Simulator NS2/NS3  Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC, STM32 and ESP32.  IDEs like Keil MDK V5, ATmel studio and MPLab XC8.  PLCs / SCADA  PCB Designing Proteus, Eagle, KiCAD and Altium  IOT Technologies like Ethernet, GSM GPRS.  HTTP Restful APIs connection for IOT Communications. Also, we have good command over report writing, I can show you many samples of our previous reports. Kindly consider us for your project and text me so that we can further discuss specifically about your project's main goals and requirements.

@electronicsdone

Best Verilog & RISC-V RTL Design Expert ⭐⭐⭐⭐⭐ Hi, Thank you for posting your project, “SystemVerilog RISC-V FPGA Implementation.” I’ve reviewed your requirements in detail and can help you correctly re-implement the IMMED_GEN and BRANCH_ADDR_GEN modules so that your simulation output fully complies with the RISC-V ISA specification and matches the expected waveforms in Vivado. I bring 11+ years of experience in digital design, SystemVerilog RTL development, CPU datapath design, and FPGA-based simulation workflows. I’ve worked extensively with RISC-V instruction encoding, sign-extension rules, and control/datapath logic, including debugging exactly the kind of immediate-format and bit-alignment issues you’re encountering. ✅ How I’ll Help You Succeed 1. Re-implement the IMMED_GEN module from scratch with correct bit extraction, sign extension, and alignment for all five RISC-V immediate formats (I, S, B, U, J). 2. Implement a clean, synthesizable BRANCH_ADDR_GEN module that correctly computes JAL, JALR, and conditional branch targets, including proper shifting and address alignment. ✅ Before I Start — One Quick Question: Would you like me to strictly follow your existing module interfaces, or am I free to slightly refactor signal naming/structure as long as the testbench passes unchanged? If you share that, we can align quickly and get this resolved cleanly. Best regards, Prat PCB Must Innovations

@nabeelraza1993

RISC V immediates are easy to get wrong because one swapped bit breaks sign extension and the whole waveform. Well, what I can do for you as an electronics engineer is re implement IMMED_GEN and BRANCH_ADDR_GEN from scratch in synthesizable SystemVerilog for Vivado simulation, with correct bit extraction, sign extension, and alignment for I S B U and J formats plus accurate JAL JALR and conditional branch target address logic. In fact, I designed a high power 10000 watt LED dimmer for a UK client and I also built an 8 bit SAR ADC logic in Cadence, so I’m comfortable with precise RTL level logic where bit placement and timing must match expected behavior.

@riab54

I am PhD holder have over six years of academic experience and have supervised small projects on RISC-V using Verilog. I am currently exploring SystemVerilog in parallel and am therefore interested in taking up this project.

@Shrutibimpl

Hello, I will re-implement your IMMED_GEN and BRANCH_ADDR_GEN modules from scratch using synthesizable SystemVerilog. I will focus on the exact bit-mapping of the RISC-V 32-bit ISA for each type, using replication operators for clean sign-extension to fix your current B-type and J-type errors. I will also develop the branch address logic to correctly handle PC offsets for JAL and conditional branches, along with the specific LSB clearing required for JALR instructions. To verify the fix, I will run a simulation in Vivado and provide the results to confirm the waveform matches the expected behavior for all instruction types. 1) Are you working with the standard RV32I base integer instruction set? 2) Do you have a specific testbench already, or should I create a new one for verification? 3) What is the specific error you are seeing in the B-type immediate waveform? Thanks, Bharat

@Mostafaihab1

Hi Client, I’m a Digital IC Design Engineer specializing in SystemVerilog and Xilinx Vivado. I’ve designed a full MIPS processor from scratch, including a 5-stage pipelined architecture with over 60 instructions. I can fix your RISC-V, ensuring correct immediate generation and branch/jump addresses. I’ll deliver clean, verified RTL ready for simulation.

@efanntyo

Hi there, I’m Efanntyo, a seasoned full-stack developer and AI specialist by trade, but I’ve also built a strong track record in FPGA RTL design and digital systems verification. For your SystemVerilog RISC-V FPGA implementation, I will deliver a clean, synthesizable RTL path for both IMMED_GEN and BRANCH_ADDR_GEN that you can drop into Vivado for simulation and, if needed later, synthesis. What you’ll get: - Correct extraction of all RISC-V immediate formats (I, S, B, U, J) from instruction bits [31:7], with accurate sign-extension and field alignment per the ISA specification. - Proper left-shifting and alignment for branch (B-type) and jump (J-type/JAL/JALR) immediates, ensuring target addresses are computed correctly from the base PC. - A synthesizable RTL implementation for BRANCH_ADDR_GEN that handles JAL, JALR, and conditional branches using least-risk practice for modeling combinational logic and registered PC paths. - Tight, readable SystemVerilog code with clear comments and a test-friendly API so your provided testbench can verify all edge cases quickly. - A plan to rework according to your testbench and waveform references, with iterative validation until the waveform matches the expected RISC-V behavior. Approach: - Re-derive each immediate format bit-field from [31:7] to avoid cross-format sign-extension mistakes. - Implement sign-extension as a dedicated utility to minimize mistakes across I/S/B/U/J. - Implement a compact, well-commented BRANCH_ADDR_GEN with

@abhisaini0188

As an AI-powered application developer with 10+ years of experience, I've accumulated a deep understanding of critical computational intricacies such as sign-extension and bit-field manipulation, which are precisely what your project requires. Moreover, my comprehensive knowledge of SystemVerilog coupled with my experience using Xilinx Vivado distinguishes me as the perfect candidate for your SystemVerilog RISC-V FPGA Implementation project. I have ample familiarity with RISC-V instruction encoding and possess a proven track record of producing high-quality RTL designs that function to the exacting specifications dictated by the Rigorous V Instruction Set Architecture. For me, RTL is not just about developing structured code but ensuring it also delivers accurate outputs throughout the simulation process. Thus, you can rest assured that my implementation will provide complete and precise immediate values for all instruction types. My solutions are always scalable and dependable - essential for FPGA-based projects - and I am accustomed to working in line with clients' expectations and delivering timely results. At this point, I could not be more excited to work on an undertaking as stimulating as the one you have presented. Let's not waste any more time, trust me with this task. With Regards!

@bjorkb

I have just completed a similar project. I delivered a fully synthesizable RISC-V immediate generator and branch address computation module that produced accurate sign-extended immediates and correctly aligned branch targets, verified by waveform matches in Vivado simulation. You won’t find a specialist better aligned with what you’re looking for. I understand the importance of exact immediate extraction and precise address calculation to pass rigorous teaching assistant validation and ensure simulation correctness. I specialize in transforming complex business requirements into high-converting, user-centric digital assets. I’d love to chat about your project! The worst that can happen is you walk away with a free consultation. Regards, Bjork Bronkhorst

@engrhasan01

Yes, I can fully re-implement your IMMED_GEN and BRANCH_ADDR_GEN modules in clean synthesizable SystemVerilog for Vivado, ensuring correct RISC-V bit extraction for I/S/B/U/J immediates, proper sign-extension, correct left-shift alignment for branch/jump formats, and accurate JAL/JALR/branch target address computation, so your simulation waveform matches the expected outputs; once you share the testbench and reference values, I will validate everything and deliver finalized RTL code.

@MouadMribat

I am a specialist in digital design and verification with a focus on high-reliability hardware and functional coverage. I will deliver synthesizable SystemVerilog modules featuring flawless sign-extension and bit-shuffling for all five RISC-V immediate formats, specifically resolving B-type and J-type mapping errors to ensure absolute waveform accuracy. My implementation includes robust branch target address logic with ISA-mandated alignment and AMBA AXI/AHB protocol compatibility for an industry-standard, production-ready solution. Technical Strategy & Implementation: Precision Extraction: I will resolve all issues related to the extraction and placement of immediate values, ensuring accurate computation for JAL, JALR, and branch targets. Advanced Verification: Utilizing Assertion-Based Verification (ABV), I ensure the hardware meets rigorous functional coverage requirements. Xilinx Vivado Expertise: I provide optimized RTL design, logic synthesis, and Static Timing Analysis (STA) within the Vivado environment to guarantee timing closure and simulation accuracy. Scalable Deliverables: You will receive synthesizable SystemVerilog modules designed for immediate success and long-term reusability in SoC and FPGA architectures. I am committed to exceeding expectations by providing reliable, production-ready hardware solutions that align perfectly with your technical vision.

@harshkakadiya149

Hi, I can fix your IMMED_GEN and BRANCH_ADDR_GEN modules and get your simulation passing. I have dealt with these type of issues across RISC-V instruction formats before. I'm currently doing my Master's in VLSI at IIT Bombay, and I write synthesizable SystemVerilog daily. I already have Xilinx Vivado installed and ready to go, and I've done many projects on it, including building complete RISC-V datapaths from scratch. I will completely rewrite both modules to ensure strict compliance with the RISC-V ISA specification, making sure the immediate bit extraction is accurate and the JAL/JALR/branch targets are computed perfectly against the base PC. If you send over the assignment instructions, your testbench, and the reference waveforms, I can knock this out for you quickly. I'd also definitely be interested in helping out with your future hardware projects once we get this one sorted. Let me know if you want to get started. Best, Harsh Kakadiya

@ZainAbbas51862

Greetings Dear Hiring Manager I have read the description of your project and I understand everything. As a digital logic specialist proficient in SystemVerilog and the RISC-V RV32I ISA, I will resolve your sign-extension and bit-swizzling errors to ensure your IMMED_GEN and BRANCH_ADDR_GEN modules pass all testbench edge cases. I have extensive experience debugging Xilinx Vivado waveforms and will provide synthesizable, clean RTL that perfectly aligns B-type and J-type offsets for accurate program counter transitions. I am waiting on chat to discuss more and I am willing to start it now. Best Regards, Zain Abbas