Terminé

EDA Application Tester

Décerné à:

kartikprmr

Greetings, I have 10 years of experience in ASIC/FPGA Design Verification and would like to work in this project. I have expertise following languages: VHDL, Verilog, Systemverilog/UVM, Python and Perl (To automat sim Plus

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0.0

5 freelance font une offre moyenne de ₹10222 pour ce travail

raulbehl

Hey! Please check my reviews and profile to know more about me and my work. We’ll get in touch as soon as you review the details.

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(66 Commentaires)
5.9
rubelsarkar161

Hi, I do work in electronics and VLSI field. +8801750377717 thats my contact, we can talk, lets see if I can help.... (contact: plus eight eight zero one seven five zero three triple seven one seven) thanks to in Plus

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(1 Évaluation)
2.0
xentricsoft2

Dear Prospect Hiring Manager. Thank you for giving me a chance to bid on your project. i am a serious bidder here and i have already worked on a similar project before and can deliver as u have mentioned I am a Fu Plus

%bids___i_sum_sub_35% %project_currencyDetails_sign_sub_36% INR en 7 jours
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0.0
kosadev

Hi, I am C++ developer from Poland. I have experience in programming uisng Qt framework included most modules and Qml. This is mobile app which I created [login to view URL] Plus

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0.0