Will discuss on chat. Please share a good number to call and a few time slots when you are available.
Greetings, I have 10 years of experience in ASIC/FPGA Design Verification and would like to work in this project. I have expertise following languages: VHDL, Verilog, Systemverilog/UVM, Python and Perl (To automat sim Plus
5 freelance font une offre moyenne de ₹10222 pour ce travail
Hey! Please check my reviews and profile to know more about me and my work. We’ll get in touch as soon as you review the details.
Hi, I do work in electronics and VLSI field. +8801750377717 thats my contact, we can talk, lets see if I can help.... (contact: plus eight eight zero one seven five zero three triple seven one seven) thanks to in Plus
Dear Prospect Hiring Manager. Thank you for giving me a chance to bid on your project. i am a serious bidder here and i have already worked on a similar project before and can deliver as u have mentioned I am a Fu Plus