RVLDG Paper Replication and Optimization -- 2

Replicate the reference RVLDG paper exactly in Cadence Virtuoso using 90nm CMOS technology and then develop a novel optimized version with minimum Power Delay Product (PDP). The final work must be suitable for IEEE conference publication and include all required technical content, figures, tables, simulations, and explanations. Phase 1: Reference Paper Replication Implement: 1. Conventional Domino OR Gate (CD-OR) 2. Reduced Delay Domino OR Gate (RD-D-OR) 3. RVLDG (Reference Design) Technology: • 90nm CMOS • Cadence Virtuoso • Spectre Simulator • VDD = 1V Provide: • Schematic diagrams • Testbench circuits • Transistor sizing details • Input pulse setup • Output waveforms • Power calculation • Delay calculation • PDP calculation Phase 2: Novel Optimized Design Develop a new optimized domino gate architecture based on RVLDG. Possible Novel Features: • Adaptive Keeper Control • Split Bulk-Driven Keeper • Leakage-Aware Footer Network • Weak PMOS Level Restorer • Conditional Evaluation Network The optimized design must have lower PDP than all existing previous Design of domino OR . Required Explanations For every circuit provide: 1. Circuit Description-Explain each transistor function.-Explain keeper operation.-Explain evaluation network. 2. Working Principle-Precharge phase operation.-Evaluation phase operation.-Dynamic node behavior. 3. Mathematical Analysis -Delay equations.-Power equations.-PDP equations.-Leakage equations. 4. Novelty Explanation Research gap in RVLDG Limitations of RVLDG-Proposed improvements-Expected advantages Required Schematics Provide publication-quality figures: . IEEE Paper Deliverables: Proof of research gap has to been completed and [login to view URL] abstraction components i.e RTV processes Confirm Derived optimized Architecture that involves lesser leakage power output Please include schematics tested along graphs simulations such.

Project ID: 40534984