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Troubleshooting a wireless communication system FPGA project with bugs

Requirements:

- Proficient in Verilog/VDHL and C/C++

- Experienced with Xilinx Vivado

- Experienced in debugging on ILA/JTAG

Preferred Qualifications:

- Familiar with AXI interface

- Familiar with wireless communication system

VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible light communication (VLC) system. The projects include two nodes: user and access point (AP). Both parts include transmitter end and receiver end. The transmission implements Reed-Solomon channel coding and 4PAM modulation etc. The projects are normally tested on wired connection first then on VLC wireless channel. The developing project is based on the working ones with minor modifications. The developing project has several issues:

1. The project, on wired test, runs until around 500k packets are received, then causes byte shift in the received data. The possible cause of this issue is in a PHY receiver – pre FIFO – RS decoder – post FIFO setup,

the PHY receiver was originally checking post FIFO empty signal in previously working projects, then is modified to check the pre FIFO instead. Bugs are created in this modification. Therefore, a workaround would be to switch back to check post FIFO empty. But ideally, the bug should be fixed.

2. When PHY receiver checks post FIFO empty, PHY receiver is seeing packet drops. This is possibly due to post FIFO not being emptied fast enough. A possible workaround is to slow down the transmission of in opposite direction (can be done in C code), so that microcontroller has more time on emptying the post FIFO.

3. 4PAM is implemented. For VLC wireless test, the threshold of decoding 4PAM needs to be adjusted.

4. The DC-gain needs to be adjusted for each sample rates. The system supports multiple sample rates.

5. The system supports a variable data rate (VDR) mechanism which includes a feedback logic. The system works fine when the data rate is fixed (FDR) no matter what data rate is pre-selected. But the VDR sees packet drops. A possible starting point to troubleshoot this issue is to set the VDR boundary so that it simulates FDR. Then gradually expand the boundaries so that eventually it includes all the data rates available.

6. The receiver implements a mechanism called “reflection reduction”. Basically, it subtracts a static value based on the transmitted signal strength from the received signal, so that eliminating the impact of the reflection of the transmitted signal on the received signal. The implementation needs to be verified on VLC test. The delay between the transmitted signal and the subtraction needs to be confirmed.

The RTL designer will work closely (but remotely) with engineers in VLNComm to troubleshoot in both wired and wireless tests.

Compétences : Programmation C, Génie Électrique, Electronique, Microcontrôleur, Verilog / VHDL

en voir plus : use of fpga in embedded systems, fpga loading, fpga project flow, fpga emulation tutorial, how to implement vhdl code on fpga, how to use fpga board, fpga map, fpga projects

Concernant l'employeur :
( 0 commentaires ) United States

Nº du projet : #17578796

27 freelance font une offre moyenne de $4437 pour ce travail

ahmedmohamed85

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rojuwon1222

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ducdctoandh

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xaainulabideen

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sky19130

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Manoj3050

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have expertise in Vivado Debugging since 3.5+ years

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Mohamedsaied8

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AssistSW

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maxter6

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