Functional Verification of SHA-1 algorithim using UVM -- 2

The Universal Verification Methodology (UVM) is a collection of API and proven verification guidelines written for system verilog to create an efiicient verification environment. UVM provides the best framework to achieve coverage-driven verification (CDV). CDV combines automatic test generation, self checking testbenches, and coverage metrics to significantly reduce the time spent on verifying designs. A test bench using Universal Verification Methodology is built for the verification of SHA-1 algorithim. SHA-1 is cryptographic hash function. SHA-1 produces a 160 bit (20 byte) hash value known as a message digest. A SHA-1 hash value is typically rendered as a hexadecimal number, 40 digits long. SHA-1 forms part of several widely used security applications and protocols, including TLS AND SSL, PGP, SSH.

Compétences : Programmation C, Génie Électrique, Logiciels Embarqués, Mac OS, Verilog / VHDL

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( 2 commentaires ) San Francisco, United States

Nº du projet : #15481163

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Create Reusable Verification environment using system verilog UVM. Environment contains DRIVER,SEQUENCER,AGENT,MONITOR and SCOREBOARD. Functional coverage analysis and code coverage. Relevant Skills and Experience Plus

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I am very proficient in c and c++. I have 16 years c++ developing experience now, and have worked for more than 6 years. My work is online game developing, and mainly focus on client side, using c++ under windows envir Plus

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Best Regards! Relevant Skills and Experience I am a lecturer working at Engineering Technology Faculty - VN University of Information. I already have experiences in Verification field. Please contact me if you would Plus

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