Requiring a electrical or electronics engineer with knowledge of DFT and testibility.
You will be modifying verilog code to make it testable.
Its small project. Budget is $50.
tell me what tool you are familiar with and will be using.
Tools Known: Xilinks, ModelSim, Multisim, Verilog and VHDL coding, Matlab
16 freelance font une offre moyenne de $8/heure pour ce travail
for this project VHDL/Verilog language is best and use of modelsim for simulation and the synthesis is best by the Xilinx. i am currently working on VHDL and Verilog language and xilinx as well as model sim
Dear Sir, I have extensive experience in DFT and VLSI design with over 15 years experience in the field. I can help you with this in a very professional manner.