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    1,860 verilog freelancer jobs travaux trouvés au tarif de EUR
    Systemverilog-UVM tracer S'est terminé left

    Tracer using System verilog & UVM

    €256 (Avg Bid)
    €256 Offre moyenne
    4 offres
    verilog project mips S'est terminé left

    MIPS ALU design

    €26 / hr (Avg Bid)
    €26 / hr Offre moyenne
    1 offres

    matrix multiplication using strassenalg and karatsuba alg and carry select adder

    €47 (Avg Bid)
    €47 Offre moyenne
    4 offres

    This job is ONLY for experienced FPGA - Verilog Programmers. Apply now if you have developed bitstreams for complex applications using Xilinx or Altera FPGAs. We will match your pay with your current income OR more than that (depends on qualification) + Bonus when you deliver expected results + Opportunity to work from home + Chance to work on exciting

    €13 / hr (Avg Bid)
    €13 / hr Offre moyenne
    4 offres

    Hi, I have written (in Verilog) an SDRAM controller (for a Micron SDRAM) which works perfectly. And I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller (using Micron's model). I just need a basic (but good) verification using Modelsim and Verilog.

    €92 (Avg Bid)
    €92 Offre moyenne
    4 offres
    verilog counter 2 jours left

    need to use Quratz 18.1 to create and simulate a 5 bit counter.

    €55 (Avg Bid)
    €55 Offre moyenne
    7 offres

    I am a Verilog beginner. Need help in instantiating a LUT based memory. The requirements are stated in the [se connecter pour voir l'URL] file.

    €25 (Avg Bid)
    €25 Offre moyenne
    9 offres

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €665 (Avg Bid)
    €665 Offre moyenne
    1 offres

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €167 - €500
    €167 - €500
    0 offres

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €499 (Avg Bid)
    €499 Offre moyenne
    1 offres

    Hi, I have written an SDRAM controller (for a Micron SDRAM) which does not work very well. In the other hand, I have its model (downloaded from Micron's website). I need someone who can write a testbench to verify my controller using Micron's model and fix my controller.

    €261 (Avg Bid)
    €261 Offre moyenne
    11 offres

    I have the hash algorithm that already implemented in c++ and opencl. I want to convert these hash code into VHDL or verilog.

    €554 (Avg Bid)
    €554 Offre moyenne
    23 offres
    Vivado Expert S'est terminé left

    Hello, I am looking for Vivado expert. Only bid experts in C/Python/Verilog Hope don't waste time. Thanks

    €24 / hr (Avg Bid)
    €24 / hr Offre moyenne
    9 offres

    Hi I am looking for RTL SV code for a parameterized mux which takes in input size and select line size accordingly both for one-hot coded and priority coded and it should be synthesizable.

    €102 (Avg Bid)
    €102 Offre moyenne
    3 offres

    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

    €1491 (Avg Bid)
    €1491 Offre moyenne
    8 offres

    ...and friendly working environment - Flexible working hours - Option to learn during working hours (the 90/10 rule) WE REQUIRE: - Advanced knowledge of at least one HDL (VHDL/Verilog/SystemVerilog) - Analytical thinking, self-sufficiency, team collaboration - Advanced English (CEFR level B2 or higher) - Advanced knowledge of computer systems and architecture

    €1132 (Avg Bid)
    €1132 Offre moyenne
    13 offres

    I need someone having expertise in verilog to enhance a processor design to carry out more instructions using Quartus prime software. Further details will be provided. Deadline 3 days. Thanks

    €95 (Avg Bid)
    €95 Offre moyenne
    6 offres

    Development of a Fpga-miner and the Host mining App. The communication between FPGA and Host App is USB. Details we can discuss in private chat

    €662 (Avg Bid)
    €662 Offre moyenne
    1 offres

    ...Output LCD + LCD controller datasheet + init code will be provided. Development board will NOT be provided (you should have your own). VHDL is preferred but not obligatory, Verilog can also be used. Altera family devices should be used. Project should be oriented towards low power and low cost since day 1. Information about further requirements (some

    €685 (Avg Bid)
    €685 Offre moyenne
    9 offres

    - Need to develop bitstream for different algorithm for FPGA boards. - Developer with proven experience with FPGA Verilog. - Can able to code, simulate, synthesize and compile verilog on FPGA. - Would be great if understands concept of Blockchain technology and how it works. - Understand requirements and based on that able to prepare hardware requirements

    €14 / hr (Avg Bid)
    €14 / hr Offre moyenne
    11 offres
    VHDL or Verilog program S'est terminé left

    I need you to develop a Vhdl or Verilog program for image similarity search, by using locality sensitive bloom filter for fpga

    €16 (Avg Bid)
    €16 Offre moyenne
    1 offres

    I need to convert a python code to vhdl code using myhdl.i will attach the python code.

    €20 (Avg Bid)
    €20 Offre moyenne
    2 offres

    Hi. I am looking for a writer who can write me a short report about hiring a range of different services. Each consumer guide will have the the following guide What is xxxx 5 Common misconceptions about xxx 5 Things you should look for in a xxx 7 Questions to ask your xxxx 10 Ways you’re getting ripped off with xxxx The topics will vary but will be service based businesses - book ghost...

    €27 (Avg Bid)
    €27 Offre moyenne
    29 offres
    Create jobs website S'est terminé left

    - Persons looking for job can load CV's . Attach file and fill up informations . ( account creation needed ) - Recruiters can search CV's database looking for candidates. - CV introduction if for free , recruiters can browse anonymous Cv's for free but need to pay to get candidates full details and Cv's . - instant chat between members .

    €486 (Avg Bid)
    €486 Offre moyenne
    45 offres

    ...Evaluating its speed, throughput, area, power consumption, and energy efficiency and comparing the results to Grain-128 and Trivium. I am looking for a candidate expert on VHDL/Verilog and with a Virtex-5 board to work on ISE 14.7. We will use ModelSim and Xilinx ISE tools in this project. The deliverables will be: a. code b. testbenches c. measurements

    €149 (Avg Bid)
    €149 Offre moyenne
    3 offres

    more details will be given in the chat only serious expert and my maximum budget for this task is $100

    €49 (Avg Bid)
    €49 Offre moyenne
    24 offres

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €910 (Avg Bid)
    €910 Offre moyenne
    4 offres

    The task is to develop the implementation of the keccak256 algorithm for FPGA XILINX xcku035-1ffva1156c. Verilog / VHDL development language (Xilinx Vivado Design Suite) Functional check on any available board. Requirements for implementation: 1. The algorithm should work in accordance with [se connecter pour voir l'URL]; a. The source can

    €552 (Avg Bid)
    €552 Offre moyenne
    3 offres
    find fpga projects S'est terminé left

    Hi somebody needed for find fpga (verilog-vhdl) remote projects I paid 20% commission for each project

    €408 (Avg Bid)
    €408 Offre moyenne
    10 offres
    Matlab Codnig S'est terminé left

    I need the matlab developer and verilog developer

    €550 (Avg Bid)
    €550 Offre moyenne
    17 offres
    16-point FFT S'est terminé left

    verilog code for radix-4 16 point fft

    €13 (Avg Bid)
    €13 Offre moyenne
    8 offres
    Jobs news post S'est terminé left

    Please contect new website buld

    €3 / hr (Avg Bid)
    €3 / hr Offre moyenne
    9 offres

    i want a verilog coding regarding radix-4 16 point FFT. so i need expert help.

    €14 (Avg Bid)
    €14 Offre moyenne
    4 offres

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €10448 (Avg Bid)
    €10448 Offre moyenne
    2 offres

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €9438 (Avg Bid)
    €9438 Offre moyenne
    1 offres

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €789 - €796
    €789 - €796
    0 offres

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €779 - €779
    €779 - €779
    0 offres

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €780 - €780
    €780 - €780
    0 offres

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €824 (Avg Bid)
    €824 Offre moyenne
    3 offres

    ...for experienced FPGA programmer with Verilog skills that can develop bitstreams for BCU1525 (Xilinx VU9P) deployable on the Minerator shell. Equihash variants and X.. variants (x16r - requires changing two BCUs) would be highest priority. Answer me those question--> You must --> have access to BCU1525? And Verilog experience? which Bitstream would you

    €649 - €779
    €649 - €779
    0 offres

    Dear Translators, I am looking for Lithuanian translators for regular work for one of our Pharmaceutical client. I have attached the first file of 1600 words and I can offer $0.02-0.03 per word so please quote accordingly. The best bid with proven experience will be awarded the project. Thanks

    €723 (Avg Bid)
    €723 Offre moyenne
    8 offres
    reviewing a code S'est terminé left

    hi all how are you? this is a verilog question whats output base on testbench? the codes are in txt file

    €46 (Avg Bid)
    €46 Offre moyenne
    1 offres

    CS 223 Digital Design: Smart Evacuation Elevator (System Verilog) Ödevin 21 Aralık 2018'e yetişmesi gerekiyor. Ödev hakkında bilgi için lütfen iletişime geçiniz.

    €132 (Avg Bid)
    €132 Offre moyenne
    3 offres
    LUT optimization of FFT S'est terminé left

    Need to implement 16 point FFT in Verilog (Xillinx) , and use memory based LUT optimization , using the research paper attached to optimize the 16 point FFT, and compare the Area and Timing of both the optimized and un-optimized implementation. Will need a small write-up comparing both the results , complete source code of both the implementations.

    €136 (Avg Bid)
    €136 Offre moyenne
    6 offres
    Verilog Expert S'est terminé left

    I need urgent work requires Verilog expertise. It also includes a short report. More details on chat.

    €54 (Avg Bid)
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    20 offres

    I need to design a 4 bit adder in verilog. I will provide more details in the chat.

    €31 (Avg Bid)
    €31 Offre moyenne
    6 offres

    Hello everyone, i have some jobs about writing, they are easy to finish, i can offer many jobs like this. If you are interested in writing, then come to me, please. Thank you very much..

    €17 (Avg Bid)
    €17 Offre moyenne
    77 offres

    Objective is to develop one VLSI Architecture and Verilog code for Algorithm-1(2D-SRNCP) [1] with Derivative variance correlation map for given two 256*256 synthesized & one SAR real time image. Implementation should be done in Matlab@Simulink and Xilinx@ System Generator environment. Implement above algorithm on FPGA Board & GPU. Simulation results

    €124 (Avg Bid)
    €124 Offre moyenne
    2 offres

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €78 (Avg Bid)
    €78 Offre moyenne
    5 offres