Read data adc fpgaemplois

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    2,665 read data adc fpga travaux trouvés au tarif de EUR

    Je travaille sur la programmation d'une imprimante 3D sur Le FPGA, je voudrai avoir de l'aide, Mon projet consiste a Controller 3 moteur pas a pas pour dessiner sur un sol mobile avec un moteur au milieu pour envoyer de plastique fondu

    €32 - €270
    €32 - €270
    0 offres
    Altera FPGA PCIe card S'est terminé left

    Altera FPGA PCIe card main chip: Altera Cyclone IV CGX functions: ADC/DAC, PCIe 1.1 x4, DDR2,

    €656 - €1312
    €656 - €1312
    0 offres
    FPGA design S'est terminé left

    multipliers

    €242 (Avg Bid)
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    1 offres

    The parking system has 4 levels, level 1 for admins and disabled, level 2 for staff and disabled, level 3 for visitors and disabled, level 4 for visitors.. we two gates in each level (the gate is a pair of IR sensor) , one gate for entrance and the other for exit.. moreover we have camera and monitor near the entrance gate of level 1 , the camera detects the type of car that entering the parking a...

    €140 (Avg Bid)
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    5 offres

    ...deconding and encoding. this will be run on an MyRIO unit so should either be written for this or easily ported from another DAQ system. Ideally it would utilise the RT Module and FPGA Module and operate with as little overhead as possible. The VI should be able the, in terms of the decoder, output a string or timestamp with the current real time LTC timecode

    €357 (Avg Bid)
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    Design adc data decoding module. (vivado 2018.2) Input: FCLK,DCLK,DATA_0~DATA_15.(all input signals are LVDS) Output: CLKOUT, DOUT_0 [15:0] ~ DOUT_31 [15:0]. One data path contains two adc signals. The two adc signals are distinguished by FCLK level. I need to decode the adc data into 16-bit wide data and output a total of 32 channels of a...

    €174 (Avg Bid)
    €174 Offre moyenne
    4 offres

    How does the parking system work? The p...that i am authorized to park only at level 2 and there is only for example 7 vacant lots for staff in level 2. The system is : FPGA ;Nexys 2 spartan 3E, Camera connected to the FPGA, And the monitor connected via VGA to the FPGA, The gates(pairs of IR sensors) in a bread board as illustrated in the abstract.

    €670 (Avg Bid)
    €670 Offre moyenne
    3 offres

    Need help program FPGA with Artix-7 using Verliog.

    €109 (Avg Bid)
    €109 Offre moyenne
    5 offres

    VHDL, LTE,WiMAX,Bluetooth,RF,FPGA

    €17 / hr (Avg Bid)
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    3 offres

    ARM firmware with LINUX for DE10-Nano board A. Play with the evaluation board 1. Project Owner will provide a P0496 ARM Processor base on Cyclone V SE FPGA computer board (DE10-Nano board). The board will have Ethernet port and SD card. 2. Developer needs to prepare LINUX Kernel to run on embedded computer board with Ethernet TCP/IP to connect with

    €3520 (Avg Bid)
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    22 offres

    Necesito obtener mediciones de un PIN de la tarjeta y mostrarlos en la PC usando DMA.

    €91 (Avg Bid)
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    3 offres

    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

    €153 (Avg Bid)
    €153 Offre moyenne
    1 offres

    Implement the Zen Protocol in the FPGA and update the Mining App

    €1067 (Avg Bid)
    €1067 Offre moyenne
    3 offres

    Need help program FPGA to communicate with TI7200 through SPI, and generate 300 and 100 Hz sine waves to drive two electric coils,

    €424 (Avg Bid)
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    12 offres
    FPGA Designing 2 jours left

    Hello, I need FPGA designing expert. I have complete details of the project. Place your bids, i will share the details with the best bidder. Thank you in advance

    €49 (Avg Bid)
    €49 Offre moyenne
    11 offres

    We have an in-house trading application which we intend to move to FPGA, using metamako or solarflare fdk

    €70 / hr (Avg Bid)
    €70 / hr Offre moyenne
    1 offres

    Its a small assignment. If you are an expert and have worked on it before. text me

    €113 (Avg Bid)
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    9 offres

    Hi TIV LAbs, I noticed your profile and would like to offer you my project. We can discuss any details over chat. Have you worked on the nexys 4 ddr fpga board?

    €32 (Avg Bid)
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    1 offres

    build a matlab simulation of pmu without time stamping for 1 phase use recursive algorithm for [se connecter pour voir l'URL] each sub system like adc etc

    €43 (Avg Bid)
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    6 offres

    ...looking for someone who can design a FPGA based X13bcd miner to mine X13bcd based coins like BCD. The design should be adaptable for possible changes in the X13bcd algorithm. Use vivado or other software make bitstream for vu9p fpga card with pcie,like xilinx vcu1525. make a miner software for ubuntu or windows. FPGA should be capable of mining with

    €2011 (Avg Bid)
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    The main aim of the project is to design and simulate a Blackjack game model using VHDL and demonstrate it using Alter Cyclone V SoC. The inputs are taken from the play...demonstrate it using Alter Cyclone V SoC. The inputs are taken from the player using the switches and push buttons while the output is displayed on the 7-segment display of the FPGA.

    €325 (Avg Bid)
    À la une
    €325 Offre moyenne
    3 offres

    1. Design platform: VIVADO 18.2 2...xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 ...

    €163 (Avg Bid)
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    Use the following components to build a small SMPTE Timecode reader / generator: Functions: 1) Read LTC input through 3.5mm Audio jack. 2) Output LTC via 3.5mm Audio jack (Use the same port for bi-directional). 3) Retain the synched Timecode with an RTC without slippage. 4) Display the Timecode constantly on the OLED display. 5) Sync Between two Similar

    €207 (Avg Bid)
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    5 offres
    Solving FPGA output module S'est terminé left

    1. Design platform: VIVADO 18.2 2...xcz7020CLG484-1 3. language: Verilog 4. Input is all lvds, fclk is frame clockwise, DCLK is data clock, DDR mode Data receives 16 pairs of ADC data. A pair of LVDS DATA inputs 2 channels of ADC data. FCLK is channel A data when it is high and channel B data when it is low. Output data with 32 ...

    €131 (Avg Bid)
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    6 offres
    STM32L031 firmwaere setup S'est terminé left

    ...basic basic. The firmware needs to initialize GPIO, ADC and Timers. Then in a main while(1) loop, capture 7 analog values from the ADC (running in DMA mode) and apply a user value to the two Timer PWM outputs. Use the attached STM32 cube configuration file for details on which pins are GPIO/Timer or ADC. Only bid for the job is you have experience with

    €109 (Avg Bid)
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    3 offres

    Need to Build the FPGA to HPS DMA code in Arria 10 Intel-Altera FPGA

    €343 (Avg Bid)
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    2 offres
    fpga pattern generator S'est terminé left

    fpga pattern generator connected to a pc starting from an evaluation board and an HDL from TI.

    €267 (Avg Bid)
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    Nordic NRF52 Firmware S'est terminé left

    ...peripherals. Has functions to read/write I2C data to/from the IR Thermometer, Heart Rate & Pulse, Accelerometer, Gyro, Compass, ECG Clock, and Battery Charger. Has functions to read/write 4-wire SPI to/from the ECG sensor Has functions to read I2S data from MEMS microphone Has functions to read ADC value for Glucose Monitor ...

    €974 (Avg Bid)
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    9 offres
    FPGA Project 2xI2S to SPI S'est terminé left

    Project target is to have a FPGA to communicate with two I2S codecs and to provide a SPI slave connection conveying the I2S data to and from a local MCU. Testing scripts and test timings for the Altera Quartus environment are required. For the proper testing of the project deliverables, test scripts and test timings need to be created and relevant

    €122 (Avg Bid)
    €122 Offre moyenne
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    Video Compression Using FPGA S'est terminé left

    I need to perform video compression using FPGA My final aim is to get a .bit or to .bin file so that I can burn the image to my fpga and simply voila.. Kindly visit this link in order to get an insight to the board that I will be using… [se connecter pour voir l'URL] I want video to

    €138 (Avg Bid)
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    I have my FPGA Xilinx Artix 7 XC7A50T development platform for my personal project. It has DDR3, Hi-speed ADC, Hi-speed DAC, UART, SPI(x2), IIC, and an Ethernet MAC. I need a complete design with microBlaze. I can provide a small example xpr prj but not yet finished. I need someone to configure and link the ip together and have it finally synthesis

    €164 (Avg Bid)
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    9 offres
    Vhdl code modifications S'est terminé left

    Need a vhdl expert for Vhdl Code modification. Clock divider and counter design. Code needs to be run on an fpga. Thanks

    €19 (Avg Bid)
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    12 offres

    I'm trying to port PYNQ over to a diligent board that is not directly supported. I'm hoping somebody has already done this that would be willing to share their SD card files with me to save me the trouble. I'm looking for PYNQ version 2.2 or 2.3. Please and thankyou.

    €125 (Avg Bid)
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    ...myself, I need help in writing and the circuit diagram and the code, the code to use can be python or C programming or Embedded system using the LED, solar panel, Amplifiers, ADC, MUCs Objectives Objective 1- Develop a prototype of the VLC and showcase the effectiveness by using LEDs.‎ Objective 2- To presents the comprehensive experimental work on

    €222 (Avg Bid)
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    D Class Amp S'est terminé left

    Design of a D class amp. Digital Input to DAC from FPGA . VHDL files for Digital Input will be provides. Amplification part of the circuit to have a Mosfet setup. DAC and Mosfets have been selected. Full circuit simulation to be done in Tina software.

    €231 (Avg Bid)
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    Hello, I have developed the full game in verilog, but I need help with a game over screen to pop up with the player loses all of his lives or a win screen with the player has beaten the game. I will provide you with all the code, mifs, rams, and I just need help to implement the win and game over screens.

    €204 (Avg Bid)
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    3 offres
    ProjectDone S'est terminé left

    The project is over VHDL using Vivado software, and it contains five smaller parts. have a fun with FPGA and hardware language.

    €16 / hr (Avg Bid)
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    build a phasor calculator S'est terminé left

    build a phasor calculator in simulink to display voltage current and [se connecter pour voir l'URL] should have input filter,ADC block,DFT,sequence analyzer and display voltage current pf lag or lead

    €204 (Avg Bid)
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    4 offres
    abiramiamanm S'est terminé left

    vlsi coding using QUARTUS II software FPGA

    €17 (Avg Bid)
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    We are looking for an implementation of a FPGA SATA-to-SATA bridge. Design should be made in VHDL and be compatible to Xilinx Aritx-7 Series. The FPGA should receive SATA as a device (SATA device controller) and forward these information after processing to one or two SATA devices as SATA host (SATA host Controller).

    €2922 (Avg Bid)
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    Programacion en Verilog -- 2 S'est terminé left

    ...de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su validación experimental se realizará en el laboratorio mediante una aplicación sencilla propuesta por cada grupo que haga uso de los recursos hardware

    €199 (Avg Bid)
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    Digital To Analoge S'est terminé left

    ...company in development of Electronics, to run Piazo Printhead. I am looking for a engineer with experience in sending Digital Data to a DAC setup and amplified via Mosfets. Digital Data will be implemented on a Xilinx FPGA. Trapezoidal waveform needs to be written in VHDL so that circuit and Code simulation can be done in Tina software. An explanation

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    Develope script in XILINX ISE FPGA using nexys 4 ddr card Language VHDL For calculator

    €38 (Avg Bid)
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    Programacion en Verilog S'est terminé left

    ...de la arquitectura del juego de instrucciones del RISC-V. El microcontrolador debe ser descrito en SystemVerilog de modo que sea sintetizable y pueda ser implementado en una FPGA Cyclone IV de Altera. Su validación experimental se realizará en el laboratorio mediante una aplicación sencilla propuesta por cada grupo que haga uso de los recursos hardware

    €212 (Avg Bid)
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    4 offres
    Update Miner for FPGA S'est terminé left

    Need to update VHDL and C-Code for change the communication from PCI-e to USB. The target is a Xilinx FPGA

    €548 (Avg Bid)
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    We are Hiring Good Programmer in FPGA, GPU, CUDA, MATLAB for our Company. (Removed by Freelancer.com Admin)

    €321 (Avg Bid)
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    The project is described in the uploaded file, however one can alter the project as long as keeping the equipments and the goal of the project intact

    €121 (Avg Bid)
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    Check hardware schematic S'est terminé left

    ...wattmeter can turn on/off the current flow. -The ESP8266 will be programmed using a USB to TTL adapter. -It has 2 ways of measure the current (using integrated ADC in ESP8266, or using an external ADC). I need someone to verify the circuit has no errors. Additionally, I need suggestions on how I can improve it to reduce costs. Please, tell me how are

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    ...their signal to an ADC so it provide the values to one of the pins of the raspberry pi. the use of the 16 sensors will be like buttons to an old mobile phone ( read the value, and when the pass a thresshold, consider it as key press). 12 of them for numbers 0 to 9, *, # and 4 buttons on the right with special functions ( send, read, clear, backspace)

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