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    1,402 freelance verilog jobs travaux trouvés au tarif de EUR
    Systemverilog-UVM tracer S'est terminé left

    Tracer using System verilog & UVM

    €257 (Avg Bid)
    €257 Offre moyenne
    4 offres
    verilog project mips S'est terminé left

    MIPS ALU design

    €27 / hr (Avg Bid)
    €27 / hr Offre moyenne
    1 offres

    Complete a design that includes most of the elements to be used in the CPU

    €122 (Avg Bid)
    €122 Offre moyenne
    7 offres
    Verilog code 4 jours left

    Please do what is in the paper and hand me the code, testing waveforms and synthesized diagrams

    €90 (Avg Bid)
    €90 Offre moyenne
    5 offres

    I need someone to write verilog code and also test .do files for a maze game. The program should output to vga. The rules of the game are simple. You start at a point and have to figure out how to get to the exit just like an actual maze. However, there is a monster chasing you and if he catches you, you are dead. The player's movement should not be

    €154 (Avg Bid)
    €154 Offre moyenne
    4 offres
    8-bit Calculator 1 jour left

    A calculator has to bee designed using System Verilog. It includes designing ALU, memory and system controller.

    €128 (Avg Bid)
    €128 Offre moyenne
    2 offres

    I need someone to write verilog code and also test .do files for a simplified board game. The program should output to vga. the game is quite simple ;2 players roll dice and move x amount of squares according to the number rolled. first to the end of the board wins. We can discuss the details. The vga display should be very simple and custom made --

    €137 (Avg Bid)
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    2 offres
    Matlab to Verilog 13 heures left

    Code needs to be ported from Matlab to Verilog

    €105 (Avg Bid)
    €105 Offre moyenne
    5 offres

    Verilog Task with Vivado and Quartus 2. Should be familiar with schematic design in Altera Quartus 2.

    €34 (Avg Bid)
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    5 offres

    ...with MAX10 10M50DAF484C7G FPGA * ____________ Final Products: ____________ -A software-level block diagram showing the connections between the System Verilog modules described in pdf -System Verilog implementations of the modules described in pdf. -Valid hardware output. Final Note: Please attach any necessary files with a brief description of the

    €27 (Avg Bid)
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    1 offres
    Thunderbird Turn Signal S'est terminé left

    1) Design a Finite State Machine (FSM) using Verilog to control the taillights of a 1965 Ford Thunderbird. 2) Implement your design on FPGA

    €145 (Avg Bid)
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    3 offres

    ALU Design as per instructions in Verilog Task . Simulation done using Icarus VERILOG

    €19 (Avg Bid)
    €19 Offre moyenne
    11 offres

    I need someone to create video tutorials for VLSI design from basics to advanced concepts. Advanced Digital Design Concepts CMOS Logic fundamentals RTL Design with Verilog HDL's ASIC Design Systhesis Concepts ASIC Design Stratagies Static Timing Analysis Low power design implementation Design and power Constraints Perl/Shell Scripting EDA tools usage

    €425 (Avg Bid)
    €425 Offre moyenne
    7 offres

    Need someone who has the tools and/or ability to convert a relatively simple verilog (.v) file to liberty timing (.lib) format, and who can verify the resulting .lib file. If successful and painless, there will be more such projects.

    €53 (Avg Bid)
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    3 offres

    It is required to implement the lyra2z cryptographic algorithm on the FPGA. Series FPGA Ultrascale Kintex language Verilog. [se connecter pour voir l'URL]

    €574 (Avg Bid)
    €574 Offre moyenne
    9 offres

    Hey, I need help with Verilog / Vivado FPGA project. I'll send you details.

    €22 (Avg Bid)
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    14 offres
    Verilog/Vivado FPGA Help S'est terminé left

    Hey, I have a project that needs to be done in Verilog and Vivado and I'll share details to anyone interested.

    €22 (Avg Bid)
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    8 offres

    Just need to design the Snake Gane as per my specifications. I am using Nexys 4 development board.

    €50 (Avg Bid)
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    6 offres

    Snake Game : 1.) Should run on Altera DE2 Board or on basy3 . 2.) Should Support VGA. 3.)Needed in a 3 days. skills:- verilog software:vivado i need this project in verilog and not in VHDL

    €69 (Avg Bid)
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    5 offres
    Task on verilog 3 bit ALU S'est terminé left

    Task on verilog 3 bit ALU Deadline 1 day Amount USD 40

    €56 (Avg Bid)
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    22 offres

    Need a small task on 3 bit ALU using verilog. Deadline 18 hours amount usd 30 .

    €25 (Avg Bid)
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    3 offres
    Distance using FPGA S'est terminé left

    I work in the Electrical Engineering Field. The project is to create a distance measuring program using verilog. I will be using Basys 3 ( FPGA) and an Ultrasonic sensor ( HC-SR04). The idea is to measure the gap between two vehicles. The sensor will be placed in the front of a toy car and used to measure the gap instantaneously and also save that data

    €104 (Avg Bid)
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    21 offres

    I would like to discuss with freelancers having strong expertise in programming languages like VHDL, Verilog, Matlab, embedded C Please reach out to me. Engineering B.Tech. is must

    €14 / hr (Avg Bid)
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    30 offres

    I have project ready already just need some help!

    €172 (Avg Bid)
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    9 offres

    Hi guys, I've done a simple design to test the SRAM of Digilent Cmod A7 FPGA board. This is how it works: Using a terminal through UART, I send the input data and address to the SRAM. Then I send address where to read, and I get back the data previously written. Everything works OK except the controller. I need someone to review my design and fix it.

    €17 (Avg Bid)
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    6 offres

    Any encryption code (AES/RSA) written in VHDL/Verilog in Quartus II for fpga board stratix IV. Please contact for more details.

    €29 (Avg Bid)
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    3 offres

    we need a technical content writer who knows the system Verilog, OVM and UVM.

    €127 (Avg Bid)
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    7 offres

    This is pavan. I am from the VLSI industry. I need a technical writer to explain 3 subjects(digital electronics, Verilog, and VHDL).

    €110 (Avg Bid)
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    17 offres

    We are looking for C++ programmer with experience in building GUI using QT. Preferable EDA/ Verilog Experience with background in Electrical Engineering

    €443 (Avg Bid)
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    15 offres

    Please refer the att...the attached document. This is the base paper of my project. I want to do my project on 64 bit square root carry select adder. I request you to help me with the coding in Verilog using Xilinx in gate level or switch level modelling. Can you please share the cost and the time line for the code. I will need it as soon as possible.

    €38 (Avg Bid)
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    13 offres

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €154 (Avg Bid)
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    12 offres

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €131 (Avg Bid)
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    4 offres

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like ...Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

    €363 (Avg Bid)
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    2 offres
    DSP48E1 help S'est terminé left

    Hi! I need some help with DSP48E1 verilog instantiation.

    €3 / hr (Avg Bid)
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    5 offres
    I want clients S'est terminé left

    I need some help with selling my services. I am verilog/ matlab coder and I need customers . you find me a client , I write his/her code and you get paid %30 of the project budget

    €20 (Avg Bid)
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    1 offres

    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

    €135 (Avg Bid)
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    7 offres

    ...i am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but

    €34 (Avg Bid)
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    110 offres
    verilog project S'est terminé left

    verilog coding using putty or terminal. if you are interested i will give more information.

    €119 (Avg Bid)
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    27 offres
    System verilog S'est terminé left

    I want help with system Verilog coding. I have a working code that I want revised a bit.

    €86 (Avg Bid)
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    8 offres
    verilog project S'est terminé left

    mtech Verilog project

    €19 (Avg Bid)
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    19 offres

    looking for someone who can convert Open CL algorithm into FPGA Verilog project

    €159 (Avg Bid)
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    7 offres

    Only experienced developer in FPGA mining and OpenCL GPU mining. I am looking for a freelancer who can convert Open CL algorithm into FPGA Verilog project.

    €2505 (Avg Bid)
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    15 offres

    my company is going to build a website for the asic verification. we need a technical content writer who knows the Verilog, system Verilog,uvm and ovm industry subjects.

    €92 (Avg Bid)
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    12 offres
    Hough transform in Verilog S'est terminé left

    implement Hough transform algorithm with FPGA with verilog in ISE input = 8*8 binary image

    €89 (Avg Bid)
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    2 offres

    ...the mics into FPGA-board, and stream this recording to either SD-card or as some other type of output. I need consulting about the possible output-types, and then the HDL/Verilog coding to do the recording, convert PDM-to-PCM (16 bit) and output all 6 microphones Not sure I will be able to supply a remotely-accessible computer connected to the FPGA+mics

    €18 / hr (Avg Bid)
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    9 offres
    verilog assignment S'est terminé left

    Hello, i need help with an assignment for verilog. Specifically I need to continue with an RISC-V ALU that I am required to make. Then after I am done with the executions, I need to make a Fetch, Decode and Writeback code. We can talk so I can explain more of the files given to us and for any questions. Some is the work that I have done so far. I am

    €116 (Avg Bid)
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    12 offres

    Requirements: - Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible

    €3926 (Avg Bid)
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    27 offres

    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    €345 (Avg Bid)
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    3 offres

    Verilog expert required for task on Digital Systems Deadline 2 Days Budget 30 usd. Details will be shared with interesting bidders

    €58 (Avg Bid)
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    18 offres