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    1,765 freelance verilog jobs travaux trouvés au tarif de EUR

    Tracer using System verilog & UVM

    €247 (Avg Bid)
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    4 offres

    MIPS ALU design

    €26 / hr (Avg Bid)
    €26 / hr Offre moyenne
    1 offres

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €164 (Avg Bid)
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    7 offres

    Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate

    €124 (Avg Bid)
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    2 offres

    The aim of the project is to design a BIST controller to insert and detect the faults (defect) like ...Read disturbance, Erase disturbance, Program disturbance, SAF, TF, ADF, CFs, TF, NPSF, Retention fault in FLASH memory by using BIST algorithm like March algorithm using verilog or VHDL in Xilinx or Modelsim. Need Simulation waveforms for the same.

    €354 (Avg Bid)
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    2 offres
    DSP48E1 help 9 hours left

    Hi! I need some help with DSP48E1 verilog instantiation.

    €3 / hr (Avg Bid)
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    5 offres

    I need some help with selling my services. I am verilog/ matlab coder and I need customers . you find me a client , I write his/her code and you get paid %30 of the project budget

    €15 (Avg Bid)
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    2 offres

    I need to implement the project using fully parallel interleaver and QPP interleaver in FPGA platform. the language used for coding is Verilog and it is synthesized in Xilinx.

    €131 (Avg Bid)
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    7 offres

    ...i am looking for Electrical & Electronics engineer Mechanical Engineer Civil Engineer Engineers should be expert in following fields Arduino Matlab Raspberry Pi FPGA Verilog/VHDL Python PCB Design (Eagle/Altium) Solidworks AutoCAD if you are expert in any of above mentioned fields then you can place a bid. We will prefer fresh Freelancers but

    €32 (Avg Bid)
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    112 offres

    verilog coding using putty or terminal. if you are interested i will give more information.

    €115 (Avg Bid)
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    27 offres

    I want help with system Verilog coding. I have a working code that I want revised a bit.

    €89 (Avg Bid)
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    9 offres

    mtech Verilog project

    €18 (Avg Bid)
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    19 offres

    looking for someone who can convert Open CL algorithm into FPGA Verilog project

    €153 (Avg Bid)
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    7 offres

    Only experienced developer in FPGA mining and OpenCL GPU mining. I am looking for a freelancer who can convert Open CL algorithm into FPGA Verilog project.

    €2411 (Avg Bid)
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    15 offres

    my company is going to build a website for the asic verification. we need a technical content writer who knows the Verilog, system Verilog,uvm and ovm industry subjects.

    €92 (Avg Bid)
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    12 offres

    ...to keep track of what jobs they are doing and how far they have progressed. I have an incoming purchase order that is a pdf file. I need the information taken from that purchase order and transferred to another document that displays the original information plus a few extra columns indicating a start and stop time for each jobs, Total minutes spent

    €92 (Avg Bid)
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    33 offres

    implement Hough transform algorithm with FPGA with verilog in ISE input = 8*8 binary image

    €86 (Avg Bid)
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    2 offres

    ...the mics into FPGA-board, and stream this recording to either SD-card or as some other type of output. I need consulting about the possible output-types, and then the HDL/Verilog coding to do the recording, convert PDM-to-PCM (16 bit) and output all 6 microphones Not sure I will be able to supply a remotely-accessible computer connected to the FPGA+mics

    €17 / hr (Avg Bid)
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    9 offres

    Hello, i need help with an assignment for verilog. Specifically I need to continue with an RISC-V ALU that I am required to make. Then after I am done with the executions, I need to make a Fetch, Decode and Writeback code. We can talk so I can explain more of the files given to us and for any questions. Some is the work that I have done so far. I am

    €112 (Avg Bid)
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    12 offres

    Requirements: - Proficient in Verilog/VDHL and C/C++ - Experienced with Xilinx Vivado - Experienced in debugging on ILA/JTAG Preferred Qualifications: - Familiar with AXI interface - Familiar with wireless communication system VLNComm has several current working FPGA projects and one incomplete FPGA project in development on the topic of visible

    €3780 (Avg Bid)
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    27 offres

    Науково-дослідний проект в галузі неруйнівного контролю. ____________________________________________________________ Scientific research project in the field of non-destructive testing.

    €332 (Avg Bid)
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    3 offres

    Verilog expert required for task on Digital Systems Deadline 2 Days Budget 30 usd. Details will be shared with interesting bidders

    €55 (Avg Bid)
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    18 offres

    FPGA TCPIP implementation using Verilog

    €18 / hr (Avg Bid)
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    16 offres

    Verilog digital logic deisgn simple work

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    18 offres

    I have Altera Verilog source code. This is crosspoing from Altera. Add a special feature (essential) to enable any one input (DI) to connect simultaneously to ALLoutputs (DO). Likely part would be EPM570T100I5. You can get source code follow link. [login to view URL]

    €39 (Avg Bid)
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    16 offres

    I have a simple Verilog project. This is very simple. I attached a Logic diagram. Please reference this. Thanks for advance.

    €20 (Avg Bid)
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    21 offres

    I want to Verilog programmer. This job i This is very simple. I attached image for logic. You can write code on QuartusII. and then the code must be compiled. Please check image and place bid. Thanks.

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    17 offres

    Verilog and Quartus based programming. The project requires a working alarm clock with certain specifications to be met when certain switches are activated.

    €18 / hr (Avg Bid)
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    20 offres

    Program counter to be simulated with testbench and implemented on De0-cv fpga. Please see file for exact specificiations and criteria.

    €112 (Avg Bid)
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    19 offres

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display. Design Specifications for the Alarm Clock • Time should be displayed on the 6-digits of the 7-segment display (HHMMSS). o The left two digits will be the hour, middle two digits will display the minutes and the right two digits will display the seconds. (the period

    €104 (Avg Bid)
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    13 offres

    We are looking for a System Verilog Training for few Engineers in our premises.

    €1694 (Avg Bid)
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    5 offres

    Design Pipeline processor for RISC based instruction set on Xilinx ISE verilog for Spartan 3E board. Instruction set is given and we need certain kind of output based on designed assembly code. Code should be loaded on Instruction memory and it's already done. we have only 2 days for that but processor is 8bit and instruction is 16bit

    €85 (Avg Bid)
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    8 offres

    ALU The ALU should be coded using these integer operations *, +, -, and /. Register File The register file must be implemented in a separate module. Hex display The hex display must be implemented using a function that converts digits to 7 segment display segments.

    €104 (Avg Bid)
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    19 offres

    Design an Alarm Clock using Verilog and implement it on DE0-CV board using HEX display.

    €157 (Avg Bid)
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    15 offres

    i need to design 8 bit pipeline line processor in xilinx ISE. It should be in verilog. there is 3 type of instruction set.

    €73 (Avg Bid)
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    5 offres

    Hello, I need some help with Verilog coding. I already have the code but Im having errors and cant compile it. Also, I need hepl with implementing testbench. Teamviewer required to debug the code and I can send you the document to take a look at the project.

    €90 (Avg Bid)
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    11 offres

    Hi, I have opencv python programs want to implement them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYN...them on the ZYNQ SoC. To be in precise want to implement custom object detection(using opencv, tensorflow) on to ZYNQ board. And also converting the python program to VHDL/Verilog.

    €112 (Avg Bid)
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    7 offres

    - Development Environment Tool : Xilinx Vivado and SDK Latest version Device : Xilinx Zynq7045 HDL : Verilog HDL Required IP Module :HDMI_RX, HDMI_TX Using PG235 [login to view URL] Using PG236 [login to view URL]

    €109 (Avg Bid)
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    3 offres

    Hello, I have the complete knowledge of languages like shell, perl, python, verilog and system verilog.

    €61 (Avg Bid)
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    1 offres

    Hi Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members ar...Iqra Software .., I noticed your profile and would like to offer you my project. We can discuss any details over chat. How many of your team members are experienced with Verilog FPGA programing?

    €36 / hr (Avg Bid)
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    1 offres

    I need image encryption using verilog on FPGA board

    €684 (Avg Bid)
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    13 offres

    We have drivers who pick up medical specimens throughout the US. They pick up at the same locations each day. It's called a route. At the completion of their route, they must submit a picture or file copy of their route sheet that tells us what times they stopped at each clinic, and what they picked up there. Currently, they email them. It's very disorganized because they never use the c...

    €215 (Avg Bid)
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    28 offres

    I need the services of a Verilog/ Finite State Machine, Logic Control Designer/ Programmer. Good Logic synthesis is required which is basically conversion of a high-level description of design into an optimised gate-level or FSM representation. Regards,

    €25 (Avg Bid)
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    16 offres

    I need verilog code and test bench for implementing Reed Solomon (450,406) encoder and decoder.

    €480 (Avg Bid)
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    11 offres
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    1 offres

    Thank you for your service to help me getting interviews for a new full time permanent sales, management or technical jobs in Switzerland, France or Italy. Several curriculums are ready to understand better the experience, skills and details. If needed I can provide a generic cover letter. Please let'me know if you are interested and how do you manage

    €151 (Avg Bid)
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    24 offres

    Hi, I want a 2D convolution module in Verilog, using DSPs.

    €38 (Avg Bid)
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    8 offres
    Quartus Ended

    I need you to develop some software for me. I would like this software to be developed for Linux . Edit the code in FPGA Board of a printer written in Verilog language.

    €23 (Avg Bid)
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    2 offres

    I need coding VERILOG code for BMI calculation that can be run in Quartus software and burn in ALTERA DE2 board. maximum 80usd

    €90 (Avg Bid)
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    10 offres

    I have a very stable old joomla site i want accurate analytics from. I am using a relatively new open source program Matomo which has instructions on how to take the information direct from log files. It has instructions but when command line stuff comes into it I get left behind. Looking for someone to follow instructions to set this up for me. I already have the program install so you just need ...

    €635 (Avg Bid)
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    7 offres