Fpgaemplois

conception des parties commande des systèmes industrielles (FPGA , Microcontrôleur , automate programmable industrielle , Arduino .....). conception des schémas électriques.

Je travaille sur la programmation d'une imprimante 3D sur Le FPGA, je voudrai avoir de l'aide, Mon projet consiste a Controller 3 moteur pas a pas pour dessiner sur un sol mobile avec un moteur au milieu pour envoyer de plastique fondu

Altera FPGA PCIe card main chip: Altera Cyclone IV CGX functions: ADC/DAC, PCIe 1.1 x4, DDR2,

multipliers

Job Title: Subject Matter Expert (FPGA / ASIC) – Whitepaper Development We are a Europe-based strategy consulting firm seeking an experienced FPGA/ASIC Subject Matter Expert to support the development of a high-quality technical marketing whitepaper for a client in the advanced hardware engineering domain. The project focuses on communicating complex concepts in FPGA design, hardware acceleration, embedded systems, AI/edge computing, and energy-efficient algorithm implementation in a clear, compelling way for business and technical audiences. Responsibilities • Provide expert technical input for research, structuring, and drafting of the whitepaper • Validate technical accuracy of content created by our writing team • Translate complex engineerin...

I’m looking for a Mandarin-speaking professional in mainland China or Taiwan who already deals with electronic-component distributors. My immediate need is to map every FPGA, DAC, DRAM, etc. on my BOM to a locally manufactured equivalent. I’ll supply the original part numbers; you investigate, call factories, cross-check inventories, and come back with solid options that really exist on the shelf. You’ll work by the hour—research time, calls, and follow-ups count—so accuracy and speed matter. Deliverables • Excel Sheet listing each original FPGA, recommended Chinese/Taiwanese replacement, MOQ, tiered pricing, lead-time, packaging, and supplier contact details • Datasheets (PDF links in both English and Chinese where possible) &bu...

I need a simple digital circuit that lets my product handle basic signal-processing tasks using a microcontroller. A straightforward schematic and a concise bill of materials are all I’m after right now—I’m still at the early prototyping stage. Core requirements • Digital-only design focused on signal processing • Microcontroller-based implementation (no FPGA or ASIC) • Clear, well-labeled schematic in PDF or easy-to-share format • Basic firmware outline or sample code that shows how the microcontroller will manage the incoming signal Keep component choices realistic and widely available. If you’ve tackled similar low-power, microcontroller signal-processing projects before, I’d love to see an example.

I’m looking for a clean Verilog design that realises a 3-bit synchronous counter, counts in ordinary binary from 0 through 7, and drives a single seven-segment display mounted on a Zynq MP FPGA board. Everything will be built and programmed inside Xilinx Vivado, so please target the standard Zynq MPSoC constraints and make sure your files open and synthesise without warnings there. What I need from you is the complete module for the counter itself, the segment-decoder logic, a concise test-bench that proves the 0-to-7 sequence, and a Vivado project or clear instructions that allow me to generate the bitstream and dump it straight to the board. Timing must be synchronous to the on-board clock, and resets should be active-low so I can link them to a push-button. Acceptance cri...

I need a concise, synthesizable Verilog finite-state machi...in Vivado 2022.1. Please use binary state encoding; that choice is fixed for this job. Here’s how I’d like the work delivered: • Source files: top-level Verilog module, separate testbench, and any support files. • Constraints: an XDC pinout I can adapt to my board. • Vivado 2022.1 project archive, including synthesis and implementation reports. • Generated .bit file so I can program the FPGA immediately. • Short read-me explaining the state-transition diagram, how overlap is handled, and how to reproduce the build in Vivado. Acceptance is based on simulation waveforms showing correct detection, no timing violations after implementation, and successful programming of my Zynq b...

I have to count very fast digital pulses—up to 200 MHz—using a Xilinx XC7S50 (Spartan-7, BGA package). The design must implement four independent 64-bit counters that share a common asynchronous reset line brought out to a single input pin. Read-back of the counts will happen over an SPI link, so the HDL should expose a simple, register-mapped SPI slave. Alongside the synthesizable VHDL or Verilog, I also need practical guidance on the hardware: how to lay out or select a compact development board that suits the XC7S50, ensures the 200 MHz signal integrity, and brings out the reset and SPI pins cleanly. If an off-the-shelf board will work, point me to it; if a custom carrier is wiser, outline the critical constraints (clocking, decoupling, pin assignments, oscillator choice, e...

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...About Attachable secondary display for gaming/productivity: high-refresh OLED/IPS, touch + stylus, onboard compute (SoC/FPGA/AI). Works as peripheral or standalone. Role Lead HMI for the device OS. Design, prototype, and help implement an embedded UI that meets real-time limits (latency, GPU), touch calibration, and performance. Responsibilities • Core UI: launcher, menus, settings, dashboards. • Client-facing prototypes + integration. • Pipelines: Qt/QML, LVGL, Flutter Embedded, OpenGL/Vulkan. • Touch calibration, gestures, feedback. • Translate modes/sensors/AI/3D into intuitive flows. • UX research, accessibility, design system. • Sync with firmware/hardware/AI/FPGA for status/RGB/OTA. • Prototype animation/latency/power; ensure...

...can interface with. Scope • Design an original, vector-based logo that feels cutting-edge yet clean enough to reproduce on papers, slides, and the front panel of the instrument. • Create a one-page schematic or infographic that visually walks a viewer through the photon path, the hyperspectral analysis stage, and the points where the correlator links to other lab systems (e.g., spectrometers, FPGA boards, data-acquisition PCs). Essentials • The graphic language should lean toward sleek lines, subtle gradients, and a restrained colour palette—nothing ornate or overly illustrative. • Final files: editable AI/SVG Timeline I’d like first drafts within a few days and the finished assets as soon as we sign off; speed is important. When you reply,...

...Серверної частини, яка приймає файли для друку, обробляє їх і надсилає на принтер. Клієнтської частини, яка встановлюється на Windows 10+ і дозволяє користувачу попередньо переглядати, налаштовувати та надсилати завдання на друк. Reference Software — набір Python/C програм з графічним інтерфейсом для керування принтером. Принтер — це не просто друкарка, а пристрій з вбудованим процесором (PS) і FPGA, який працює під керуванням PetaLinux (ARM64). Потрібні навички: Впевнене володіння мовами python та c/c++ (читання, адаптація, відлагодження існуючого коду). Досвід роботи з linux-based embedded systems (raspberry pi, petalinux або подібні). розуміння принципів роботи сервер-клієнтних архітектур (socket, rest, json, file-based messaging). Досвід інтеграції сторо...

...the design will be a Xilinx FPGA. Around it I want to use a precision analog front-end built from the following building blocks: • Operational Amplifiers (Op-Amps) • Digital-to-Analog Converters (DACs) • A Howland Current Pump topology If you have a more elegant approach that still meets the accuracy requirement I’m open to hearing it, but the solution must remain feasible for small-batch assembly. Deliverables • Complete walkthrough of how to connect components to FPGA • Verilog/VHDL code for the FPGA, including a simple register map that lets a microcontroller or PC set each channel’s current (positive or negative) and trigger synchronous updates. • Well-commented simulation files showing stability of the an...

...correctly and interacts properly with test drivers. Deliverables Working firmware image for 100t/75t target. Source code + build instructions. Brief test report confirming CFG, BAR, and DMA functionality. Skills Needed Strong knowledge of PCIe / DMA / BAR / MSI-X / Verilog / Vivado. Experience with embedded C/C++/Verilog and firmware development and Vivado Firmware Development. Familiarity with FPGA-based PCIe devices (Xilinx or similar) is a plus. If you can fulfill this project I will possibly use you for 3 other similar projects. Legal Notice This project is strictly for legitimate driver testing and research use — not for bypassing security or anti-cheat systems. We are a small team of Cybersecurity Engineers working on an Anti Cheat option for Indie Devel...

I have raw captures from both contact (ISO 7816) and contactless (ISO 14443) EMV cards fed directly into an FPGA test rig. My objective is two-fold: complete protocol interpretation of the traces and a thorough Differential Side-channel Analysis around the cryptographic routines. For the protocol work you will decode every APDU, verify the cryptograms and give me a clear view of transaction validity. On the DSA side I expect you to pinpoint any leakage observable in the power or timing data and explain how it might be exploited. Deliverables 1. Commented HDL (VHDL/Verilog/SystemVerilog) or equivalent scripts that ingest the captured signals and output human-readable traces for both card types. 2. Clear test results showing data being captured 3. A concise report det...

I need a compact DVB packet processor written in Verilog that runs on a Lattice iCE40 FPGA. The sole task is packet filtering—specifically PID filtering—restricted to one selected PID at a time. Scope • RTL design in clean, synth-ready Verilog targeting the iCE40 HX or UP family • Functional testbench that feeds 188-byte TS packets, demonstrates correct acceptance of the chosen PID, and drops everything else. • Synthesis script (nextpnr + IceStorm or Lattice Radiant) showing timing closure at 27 MHz TS clock or better. • Resource-usage report so I can judge fit against the device’s limited LUT/BRAM budget. • Simple register or constant that lets me change the target PID before build time; run-time reconfiguration via a small wis...

We need an experienced FPGA engineer to implement a PCIe endpoint and custom DMA firmware on an Artix-7 class FPGA carrier. The end result must be a production-quality Vivado project and a working bitstream that cleanly enumerates on Windows 11 (Intel and AMD) and supports reliable bidirectional DMA for MRD and MWR flows. The candidate should be familiar with custom RTL DMA engines, PCIe TLP handling, MSI/MSI-X, and build automation in Vivado. What we are asking for Build a clean, reproducible Vivado project that targets an Artix-7 FPGA on a PCIe carrier. Preferred Vivado version is 2023.2; later versions acceptable if reproducible. Deliver a working bitstream that programs the target board and enumerates in Windows 11 on Intel and AMD hosts without device-manager e...

...correctly and interacts properly with test drivers. Deliverables Working firmware image for 100t/75t target. Source code + build instructions. Brief test report confirming CFG, BAR, and DMA functionality. Skills Needed Strong knowledge of PCIe / DMA / BAR / MSI-X / Verilog / Vivado. Experience with embedded C/C++/Verilog and firmware development and Vivado Firmware Development. Familiarity with FPGA-based PCIe devices (Xilinx or similar) is a plus. If you can fulfill this project I will possibly use you for 3 other similar projects. Legal Notice This project is strictly for legitimate driver testing and research use — not for bypassing security or anti-cheat systems....

...short documentation. Ensure the firmware enumerates correctly and interacts properly with test drivers. Deliverables Working firmware image for 35t / 75t target. Source code + build instructions. Brief test report confirming CFG, BAR, and DMA functionality. Skills Needed Strong knowledge of PCIe / DMA / BAR / MSI-X. Experience with embedded C/C++ and firmware development. Familiarity with FPGA-based PCIe devices (Xilinx or similar) is a plus. Legal Notice This project is strictly for legitimate driver testing and research use — not for bypassing security or anti-cheat systems....

I’m building a simple digital-lock proof-of-concept on a Nexys Artix-7 board using Vivado. At this stage the only feature I need is a basic lock-out mechanism—no fingerprint, keypad, or card reader yet. I already have a rough plan and can handle the introductory VHDL/Verilog myself, but I want an FPGA expert to: • Review and refine my high-level design so the lock-out logic is clean and synthesizable. • Supply or polish compact, well-commented code blocks where my initial draft falls short. • Walk me through synthesis, implementation, and on-board testing in Vivado, stepping in to debug timing or constraint issues that pop up. I’ll run the hardware on my end; you’ll provide guidance via chat or quick screenshares and, when necessary, shar...

...Knowledge of automation / configuration tools (Ansible, Terraform, CI runners). Understanding of basic FPGA or software development environments (a plus, not required). Engagement Details Type: Freelance / remote. Mode: Hourly or per-task (depending on scope). Work coordination: Tasks managed via Microsoft Teams + Planner or GitHub issues. Access method: Remote terminal via tmate (Linux) or RustDesk (GUI), always under supervision. Reporting: Short summary after each task (actions done, logs, recommendations). Start: Immediate. Example Tasks Set up RustDesk self-hosted server on Ubuntu VPS. Configure firewall and automatic backup on existing server. Install and test GitLab Runner for FPGA build flow. Prepare environment for CI automation and linting tools. Create new ...

I need a production-ready, compact PCB where a Xilinx FPGA drives a current-steering DAC that, in turn, delivers an RF signal via an SMA connector. The board must also host the clock tree, power-conditioning network, and any local memory the FPGA requires while maintaining tight signal integrity and low-jitter clocking throughout the chain. You will take the concept from block diagram to manufacturing release: selecting the exact Xilinx part, choosing a suitable high-speed current-steering DAC, sizing passives, and routing the stack-up so that high-frequency paths, return currents, and power planes stay clean. I will share detailed interface requirements, preferred form factor, and any mechanical constraints once we start. Deliverables • Complete schematic (native desi...

We are looking for a proactive and versatile assistant to support operations, travel coordination, project management, and documentation activities within an FPGA and embedded systems company. This position is primarily remote, but occasional in-person visits to our main offices or participation in business trips within Europe (mainly Italy and Germany) will be required. You’ll collaborate directly with the company founder and CEO, helping streamline daily operations, audits, and international coordination. Key Responsibilities Travel & logistics: organize flights, hotels, and transfers for business trips; manage travel expenses and reimbursements. Project coordination: track tasks, milestones, and deadlines; assist in preparing reports and follow-up summaries. Documen...

We are looking for a skilled FPGA Design Engineer with solid experience in VHDL development and FPGA toolchains (Vivado, Quartus). You will collaborate remotely using our servers and follow a structured workflow that includes version control, automated analysis, and verification. The ideal candidate is proactive, detail-oriented, and comfortable working on real FPGA design tasks, from module development to system-level integration. Responsibilities Design, implement, and verify VHDL modules for FPGA-based systems. Work with Xilinx (Zynq) and Intel (Altera) FPGA platforms. Integrate and debug high-speed serial protocols such as Aurora, SDI, HDMI, 10 GbE, and other Gbps transceiver-based links. Support signal processing and video processing implementation...

I need a RISC-V co-processor that plugs into my existing RISC-V core and dramatically speeds up convolutional layers in a CNN inference pipeline. The sole metric I care about is throughput: higher frames-per-second at the same clock. Power savings or memory tweaks are nice side effects, but raw speed is what will decide success. Target platform is an FPGA prototype, so the RTL should be synthesis-ready and resource-aware. I am comfortable with Verilog, VHDL, SystemVerilog, as long as the code is clean and well-documented. AXI4 or an equally common on-chip bus is expected for host interaction, but I’m open to your suggestion if it fits the RISC-V ecosystem better. Key points you should hit • A custom instruction or tightly-coupled accelerator port on the RISC-V CPU for...

I am seeking an experienced FPGA programmer to develop a custom hardware acceleration solution for high-speed data transfer over Ethernet. Key requirements: - Design and implement FPGA-based custom hardware for high-speed data transfer. - Utilize Ethernet protocol. - Optimize for performance and reliability. Ideal skills and experience: - Proficiency in Xilinx FPGA programming. - Experience with high-speed data transfer and Ethernet protocols. - Strong background in hardware design and optimization. Submit your approach and relevant experience.

My team is tackling a run of mini-projects centred on...you might handle include: • Translating our functional block diagrams into gate-level or HDL implementations (Verilog/VHDL welcome). • Producing simulation files and screenshots that prove the logic works (Multisim, Proteus, Quartus, ModelSim—whatever you are comfortable with). • Supplying concise notes so the rest of the team can reproduce or extend the design. If you have breadboard or FPGA experience and can show a quick demo video, that’s a bonus but not essential. When you reply, link or attach a couple of past digital-circuit projects so we can see your style and depth. We plan to start with a single small module; if the collaboration clicks, you’ll be our go-to for the remaini...

Hiring: Expert Designer/Writer for Investor Pitch Deck (Deep Tech / AI Hardware) ## Project Overview LLM Core AI, Inc. is a deep-tech startup building **on-premise LLM appliances (EdgeBox E1)** and an **FPGA/ASIC roadmap** for LLM acceleration. We will pitch to global investors in **San Francisco (TechCrunch Disrupt / Niu Ventures Summit, late Oct 2025)**. We’re hiring a **professional** to craft a **high-impact, bilingual (KR/EN) investor deck** optimized for fundraising. ## Scope * **Narrative Architecture**: Problem–Solution–Product/Tech–Market–Biz Model–Competition/Moat–Traction–Roadmap–Team–Financials/Use of Funds–Ask * **Content Creation**: copywriting (KR/EN), core messages/taglines, 30-sec elevator pitch *...

...field crosses the thresholds I will provide. Your task is to take the sensor channels, perform any filtering or calibration they require and continuously compare the results against my trigger levels. When a limit is reached, the corresponding LED must switch on with minimal latency and remain stable (no flicker from noise). You are free to choose the processing environment— firmware on an MCU, FPGA logic, or a host-side script—as long as it meets these performance expectations and works with the existing ADC stream. Deliverables • Complete source code and build files • Pinout / connection diagram for the LEDs and any required conditioning components • A short README explaining how to adjust thresholds and re-flash or redeploy the code To be ...

...hybrid—that ingests my SD signal, upscales it cleanly to Full HD, and outputs an RTMP (or similar) stream I can point to the usual live destinations such as YouTube, Twitch or Facebook Live. If you prefer another protocol that keeps delay minimal, I’m open. I am comfortable running Linux or Windows boxes and already have a decent NVIDIA GPU available, but I’ll take your guidance if a different card or an FPGA/ASIC approach will produce better real-time results. Please provide: • the upscaling method or model you plan to use (e.g., VapourSynth with AI models, FFmpeg with CUDA filters, TensorRT, Real-ESRGAN, Topaz—whatever you trust for live performance) • step-by-step setup instructions and any required scripts/config files • recommende...

I need an experienced FPGA developer to design, program, and test an SDI fiber converter. The converter should support video signal conversion for HD-SDI and 3G-SDI formats. It must have SFP and SDI input & output interfaces. Key Requirements: - Design and implement video signal processing algorithms - Program FPGA to handle HD-SDI and 3G-SDI formats - Integrate fiber optic and SDI output interfaces - Thorough testing to ensure reliability and performance Ideal Skills and Experience: - Proficiency in FPGA programming (Verilog/VHDL) - Experience with video signal processing - Knowledge of SDI and fiber optic interfaces - Strong troubleshooting and testing skills Looking for high-quality work within budget.

...and Necessity first search algorithm implementation using python then reduced coefficients constants will be given as input to rmcm block as hardcoded values in Verilog well-structured Verilog implementation of an FIR filter that follows the RMCM (Reconfigurable Multiple Constant Multiplication)architecture. The goal is strictly functional verification, so everything happens inside ModelSim; no FPGA bitstream or ASIC sign-off is required. The code must be synthesizable, but the only deliverables I need at this stage are: • Verilog source files that realise the RMCM-based FIR • A self-checking ModelSim test-bench with a small set of example input vectors and expected outputs • Simulation snapshots or log files that prove the filter’s impulse response and...

...is the only accepted interface between the wheel’s controller and the Windows workstation that will drive it. • Position feedback has to be deterministic—optical, magnetic, or any sensing method you consider reliable is fine as long as the PC always knows which filter is in the beam path. • All mechanical, electronic, and firmware design choices are open; choose whatever motors, drivers, MCU/FPGA, bearings, or housings you trust, as long as replacement parts are serviceable locally. • A lightweight Windows utility (CLI or GUI) with a simple API/command set must let me rotate forward/backward one slot and query the current slot number. Shipping source code (C/C++, C#, Python, or similar) is part of the hand-off. • On-site hand-over and initi...

...ongoing and upcoming projects. If you're passionate about solving real-world engineering problems and want to work with a dynamic, growing team, this is your opportunity! Areas of Expertise We’re Looking For: We welcome experts in any (or multiple) of the following domains: * ✅ Digital Electronics * ✅ Power System Analysis * ✅ MATLAB / Simulink * ✅ ETAP * ✅ PowerWorld Simulator * ✅ Verilog HDL * ✅ FPGA Design & Simulation What You’ll Do: * * Collaborate with our in-house engineers on project-based tasks * Deliver simulation, analysis, and modeling results * Optimize systems for real-world application * Work *remotely* and communicate via online tools *Requirements: * * Proven experience in one or more of the tools/areas listed above * Ability to work ...

I need a compact yet reliable data-acquisition design that runs on an Artix-7 FPGA and lets me capture analog signals up to about 50 MHz from 6 x AD9226 12 bit ADC's simultaneously . The goal is simple: store every sample intact to DDR3 for 500ms, and make the stored data available later by QSPI at 40MHz, or USART. Use one digital input as trigger to start AQ, one to erase full DDR3, one to select QSPI or USART. Scope of work • Build the RTL (VHDL or Verilog—your choice) that interfaces the FPGA with a suitable high-speed ADC, brings the samples into the fabric, and buffers them without loss. • Implement a storage path—on-chip BRAM, external DDR3—to hold the data until I pull it off the board. • Provide a clean, documented interfac...

I need fresh, fully-tested ODOCrypt bitstreams for every model I run—F1, F1+, F1 Ultra and F2—and a clear way to keep them current after each yearly algorithm revision. The rebuild procedure must run directly on the FPGA Blackminer Miners operating system, so please base every step and tooling choice on what is already available in that environment. Here is what I am expecting: • A separate, optimized bitstream file for each of the four models, ready to flash and mine immediately. • A concise, reproducible walkthrough that lets me rebuild the bitstreams at any future ODOCrypt fork without outside help. Document exact tool versions, command lines, and any patches or configuration flags so nothing is left to guesswork. • Proof that each file work...

...piezoelectric strain gauges will be bonded in a 6 m × 50 mm ribbon-like array. I want to sample the whole field every few milliseconds yet keep wiring down to roughly two conductors per column, so clever multiplexing or bus techniques are essential. Thickness MUST be less than 10mm, preferably less. My preference is a self-contained, dedicated data-acquisition unit rather than a microcontroller or FPGA board. That unit must excite/condition the piezo elements, perform rapid scanning, and, ideally, stream raw values to on-board storage; no real-time dashboards are needed. Data can land in binary or CSV as long as the file format is documented. Deliverables - INITIALLY, I just want an EXPERT opinion on what could practically be achieved to deliver the peak strain (i.e. no...

...Convolutional Neural Network, trained and tuned so that it can keep pace with live throughput and later be ported to an FPGA. Here is what I expect to walk away with: • Clean, reproducible preprocessing of raw pcap files into tensors suited for a CNN, with all scripts delivered. • A CNN architecture (TensorFlow/Keras or PyTorch) that zeroes in on traffic pattern anomalies rather than signature-based classes. • Training routines, hyper-parameter sweeps, and clear evaluation metrics (accuracy, recall, F1, ROC-AUC) on the official CICIDS 2018 train/test split. • Inference benchmark showing latency figures that justify real-time use; please include profiling notes that guide an FPGA hand-off. • Well-commented code, a short report explaining d...

I'm finishing my TFG on FPGA implementation, I need someone to help me with the semi-parallel architecture of a filter bank, I have the code done and the design scheme, but I need someone to review it and help me debug it if necessary, I can send you the files so you can take a look, thanks!

...PCIe endpoint (e.g., a Wi-Fi adapter). The card provides transparent passthrough of the endpoint device to the host system, while embedding an FPGA-based DMA engine capable of bus mastering, memory injection, and packet manipulation. Control of the DMA engine is performed via the PCILeech software suite, enabling flexible direct memory access operations. Functional Blocks 1. PCIe Passthrough Bridge • Provides a transparent PCIe x1 interconnect between the host computer and the attached endpoint device. • Maintains compliance with the PCIe protocol to ensure the endpoint is enumerated by the host as if connected directly. 2. FPGA Subsystem (AMD/Xilinx FPGA) • Implements custom PCIe cores for bus mastering and DMA transfers. • Supports injection of...

I'm finishing my TFG on FPGA implementation, I need someone to help me with the semi-parallel architecture of a filter bank, I have the code done and the design scheme, but I need someone to review it and help me debug it if necessary, I can send you the files so you can take a look, thanks!

...SHA-256, RIPEMD-160 and address formatting; only matching results are returned to the host. • Host API: startKey, stride, iterations, Bloom/filter blob → receive hits. • Continuous 24 / 7 operation below 150 W per board. What I need from you Submit a detailed project proposal that confirms feasibility, sketches the architecture (parallel engines, expected clock, resource use), names the FPGA family you would prototype on, and projects the ASIC performance and die size. Include milestones, cost and a timeline that lets us enter hardware testing within one month. Prior crypto-acceleration or high-speed ECC work is highly relevant, so highlight it briefly. Deliverables 1. Synthesizable RTL (Verilog or VHDL) covering ECC, hashing and filter logic 2. Ref...

I need a complete, synthesizable SystemVerilog design that turns an off-the-shelf FPGA into a real-time image-processing engine. The pipeline must handle three stages—image filtering, edge detection, and object detection—culminating in an on-device CNN that flags target objects in every frame. FPGA Image Processing 1. I need to work on a project and implement a novel idea related to FPGA-based image processing. 2. I have the following tools available: o Xilinx Vivado 2018.2 and Xilinx Vivado 2025.1 o MATLAB 2024a and Simulink o Python simulation tools. Task: • Read an image (in BMP, .hex, or .coe format). • Refer to a recent IEEE research journal (preferably from the year 2025) for guidance or inspiration. (Focus on novelty, performance (speed...

I’m expanding an FPGA project and need someone who can move comfortably between VHDL development and quick-turn Python scripting. On the FPGA side, the immediate task is to write, tidy up, and document VHDL modules, then verify them in simulation and on hardware. Alongside that, I’d like lightweight Python utilities to automate synthesis runs, manage bitstream builds, and trigger scripted tests so I can iterate without manual intervention. You’ll be handed my current repo (Vivado-based, with ModelSim testbenches) plus a short list of new features. From there I expect: • well-structured VHDL that meets timing in a mid-range Xilinx device • Python scripts (Python 3) that call the usual vendor CLI tools, gather logs, and flag errors automatically ...

I need assistance with a college project to design a Multi-Protocol Conversion Unit (MPCU) using Verilog HDL. The MPCU should convert data between SPI, I2C, and UART protocols. Requirements: - Verilog implementation for SPI, I2C, UART (both master and slave) - Top-...The MPCU should convert data between SPI, I2C, and UART protocols. Requirements: - Verilog implementation for SPI, I2C, UART (both master and slave) - Top-level MPCU module to connect all protocols - Simulation testbenches and waveforms - Final report detailing design and results Tools: Xilinx Vivado or equivalent Ideal Skills: - Proficiency in Verilog HDL and digital design - Experience with FPGA tools (Vivado/ModelSim/Quartus) - Solid understanding of SPI, I2C, UART protocols Note: Academic project; only Indian f...

I have an FPGA board attached to a Qualcomm SM8650-based Android tablet through a USB4-to-PCIe adapter. The tablet can see the PCIe slot but not the FPGA itself, so the kernel needs a new driver that will let the system enumerate, configure and talk to the board. I will spell out the exact runtime features I need once development starts, but at minimum the driver must expose reliable low-latency communication and leave enough hooks for any additional self-test or accelerated-processing routines I later request. The board model is not one of the common Xilinx/Intel/Lattice options; I’ll provide the full datasheet, BAR layout and reference HDL so you can map registers, interrupts and DMA correctly. The tablet is running a customized Android build (newer than the standard...

Objective: I am an engineer seeking an expert mentor to help me fully understand and successfully run an open-source LLM accelerator project on my local machine. The primary goal is to gain a deep, practical understanding of High-Level Synthesis (HLS) for developing FPGA-based AI accelerators. This is a mentoring and guidance role, not a standard development contract. Project Details: Paper: "HLSTransform: Energy-Efficient Llama 2 Inference on FPGAs Via High Level Synthesis" (Cornell University, 2024)   Open Source Code:()   Freelancer's Role & Responsibilities: Project Analysis & Explanation: Explain the overall architecture of the HLSTransform project, its C++ code structure (Host vs. Kernel), and the key HLS optimization techniques used

I need an experienced embedded firmware developer to create firmware for our custom hardware using Cypress FX3 (CYUSB301x). Key Requirements: - Develop firmware for Cypress FX3 using EZ-USB FX3 SDK - Implement USB Mass Storage Class (MSC) - Configure GPIF II state machine for communication with FPGA/Microcontroller - Optimize data transfer for USB 3.0 SuperSpeed (5Gbps) - Handle standard USB descriptors (Device, Configuration, BOS, etc.) - Provide well-documented and industry-standard code Skills Required: - Strong experience with Cypress FX3 SDK (C, ARM Cortex-M3) - Familiarity with USB 2.0/3.0 protocols and classes (MSC/Bulk transfer) - Experience with GPIF II configuration - Debugging tools: CyUSB3 driver, USB analyzers (optional) - Understanding of embedded systems and firmwa...