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    2,766 e1 verilog travaux trouvés au tarif de EUR
    un mini formulaire S'est terminé left

    J’ai besoin d’un très petit script de page web qui formule un lien internet composer d’un préfix (SA) statique (qui ne change pas) d’une partie (E1) dynamique qui est un ‘echo ‘ d’un champs du formulaire (F1) d’une autre partie statique (SB) et d’une fin également (E2) dynamique qui est un ‘echo‘ d’un cha...

    €28 (Avg Bid)
    €28 Offre moyenne
    3 offres
    Systemverilog-UVM tracer S'est terminé left

    Tracer using System verilog & UVM

    €217 (Avg Bid)
    €217 Offre moyenne
    4 offres
    verilog project mips S'est terminé left

    MIPS ALU design

    €25 / hr (Avg Bid)
    €25 / hr Offre moyenne
    1 offres

    Verilog code for traffic light controller.

    €22 (Avg Bid)
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    13 offres

    i want long term employee. budget is low. its simple project. if you are expert in verilog simulation, please id here

    €3 / hr (Avg Bid)
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    9 offres

    Hi, I have MATLAB simulated algorithms I need to verify these algorithms in FPGA kit so that by converting the MATLAB code to verilog hdl or vhdl.

    €271 (Avg Bid)
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    20 offres

    I need System Verilog Oops ppt with following topics in details with example code. abstract class, parameterized class, casting Polymorphism Singleton Class Singleton Object Proxy Class Factory Class

    €173 (Avg Bid)
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    1 offres

    Hi Lightcanon, I noticed your profile and would like to offer you my project. We can discuss any details over chat. Verilog

    €208 (Avg Bid)
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    1 offres
    €58 Offre moyenne
    1 offres
    Project on System Verilog S'est terminé left

    I have to design a system where a 4x4 is multiplied by 4x1 and the output is then taken in feedback. And more operations

    €64 (Avg Bid)
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    2 offres

    I am working on lattice semiconductor fpga, and a STMicroelectronic sensor, the fpga being master has to read the values of sensor (slave). I have written the code and I also have all the documents required from both lattice semiconductor and the Sensor. I have myself worked on it a lot, but I am not getting where I am going wrong, so this would be very little work to check my code and the documen...

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    5.1 Objectives The objectives of this laboratory are: • To become familiar with the Xilinx Vivado tools for the design of logic circuits. • To understand and use Verilog HDL for the design of simple combinational logic circuits. • To implement simple combinational logic circuits using the Basys3 FPGA prototyping board

    €96 (Avg Bid)
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    3 offres
    VHDL Verilog S'est terminé left

    i am looking for the expert for VHDL Verilog i will share complete details in the chat

    €19 (Avg Bid)
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    23 offres
    FPGA designer -- 2 S'est terminé left

    I am looking for FPGA designer. Recommend verilog, xilinx.

    €125 (Avg Bid)
    €125 Offre moyenne
    15 offres
    FPGA designer S'est terminé left

    I am looking for FPGA designer. Recommend verilog, xilinx.

    €85 (Avg Bid)
    €85 Offre moyenne
    13 offres
    Write a verilog code S'est terminé left

    I need to write a verilog code

    €17 (Avg Bid)
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    We are looking for an expert in Risc-V with an FPGA board. The board should be designed in Kicad. The person should have good experience in Raman spectroscopy and graphene field gate transistor technology. People who have skills with TENG and PENG are most preferred. This is a COVID-19 research initiative (Special preference to RENODE.) Skills: Electronics, Mechatronics, Bio Technology, Processo...

    €163 (Avg Bid)
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    4 offres
    Project for Saad K. S'est terminé left

    Hi Saad K., I have a whole series of simple Verilog code need to be written. First we need to ensure you and I have same hardware so that you can write code and send to me dialy to compile and we both have same results. I prefer it if we can use yosis/nextpnr on Linux - but you can suggest alternatives. The initial projects will last a month.

    €4 / hr (Avg Bid)
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    1 offres
    Project for Saddam G. S'est terminé left

    Hi Saddam G. I need someone with Lattice FPGA or similar hardware and skills, and I get the same device (ideally using the open source tool chain such as yosys/nextpnr) and programmer. Then you write simple software in small steps building it up into larger blocks. You have to send me the Verilog code daily and I compile and run it on my copy hardware to check the functions are working to expect...

    €4 / hr (Avg Bid)
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    1 offres
    Verilog coding S'est terminé left

    Write a verilog code for an CS algorithm.

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    The objective of this project is to implement Hyper-spectral Coded Aperture (HYCA) algorithm on an FPGA. 1- Design HYCA for an FPGA. 2- Finalize/Refine the design for an FPGA. 3-Implement the HYCA on an available FPGA ( DE-10 nano development kit). 4- Evaluate the performance of the FPGA implementation.

    €322 (Avg Bid)
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    3 offres
    Project for Arslan A. S'est terminé left

    Hi Arslan A., I noticed your profile and would like to offer you my project. We can discuss any details over chat. can you work on verilog

    €7 (Avg Bid)
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    1 offres
    Project for Ahmed N. S'est terminé left

    Hi Ahmed N., I noticed your profile and would like to offer you my project. We can discuss any details over chat. Do you work on verilog?

    €7 (Avg Bid)
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    1 offres
    Project for Sardar Hasnain A. S'est terminé left

    Hi Sardar Hasnain A., I noticed your profile and would like to offer you my project. We can discuss any details over chat. Verilog work

    €7 (Avg Bid)
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    1 offres
    Digital systems and verilog S'est terminé left

    Read the MPZ paper (M. Faezipour and M. Nourani, "A Customized TCAM Architecture for Multi-Match Packet Classification," in Proceedings of the IEEE Global Telecommunications Conference (GLOBECOM), (San Francisco, CA), pp. CAM01.1.1-CAM01.1.5, Nov. 2006.) posted on the course webpage. Section III explains the Multi-Match Prioritizer (MPZ) unit. The conventional (single-match) priority...

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    3 offres
    Verilog/VHDL -2 S'est terminé left

    Verilog Please solve as beginner and can you please provide the explanation of the code Deadline : 3 days ( 72 hours )

    €11 - €29
    Scellé
    €11 - €29
    18 offres
    Verilog/VHDL -1 S'est terminé left

    Verilog Please solve as beginner and can you please provide the explanation of the code Deadline : 4 days ( 96 hours )

    €17 - €40
    Scellé
    €17 - €40
    19 offres

    Budget is AUD 50 (all included). I have some questions which need to be answered. Message me for more details.

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    10 offres
    Arduino /Raspberry Pi/ ESP/ VHDL S'est terminé left

    Hello Everyone, I am looking for Electrical Engineers with strong background in following: • VHDL/Verilog, LABView/ Multisim • Microcontroller like Arduino, Raspberry Pi, FPGA, AVR, PIC and STM32. • IDEs like Keil MDK V5, ATmel studio and MPLab XC8.

    €116 (Avg Bid)
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    Build app ios swift code S'est terminé left

    Make an IOS App using swift code language (similar to [se connecter pour voir l'URL]) Requirement: - display my web (inbox me for more information) - camera and write external memory card permission. (allow the user to use a camera or post a photo directly to the web page) - Mark favorite page ( example: [se connecter pour voir l'URL]) - a separating tab for calculating interest rate (...

    €413 (Avg Bid)
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    12 offres
    Construa um projeto em Verilog S'est terminé left

    Criar um processador em verilog, contendo as especificações citadas no pdf.

    €165 (Avg Bid)
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    6 offres
    laminated_composite_deisgn_analysis S'est terminé left

    You have been assigned with the design of a composite shell for the wing of PC9 aircraft. Under Design Limit Load (DLL), the composite laminate is subjected to given ??, ?? and ???. The laminate configuration based on the aerospace design guidelines is required. Assume that zero and 90-degree plies do not contribute towards the shear strength of the laminate. Part A: Determining failure properties...

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    Verilog/VHDL S'est terminé left

    Verilog Please solve as beginner and can you please provide the explanation of the code Deadline : 24 hours

    €29 - €30
    Scellé
    €29 - €30
    2 offres
    expert help in MS excel function. S'est terminé left

    Hello, need some expert help in MS excel function. This is for my book keeping. Please see my sheet in cell E1. I use there the "'find" function to assign a number value when the string is found. It works in E1 , F2 and also in G 3. But if the string is not found it returns "#Value" that is not good as this messes up my intention of adding them up at the end of the row...

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    Video compression algorithm S'est terminé left

    Hi buddies, I am looking for a video compression algorithm for my video recording system. There may be any algorithm ( H.264/MPEG-4,HEVC, MJPEG) in RTL (verilog orVHDL) which will work on Xilinx spartan family with 30fps/60fps. This code includes the camera interface also. Because i am going to record the live video from camera upto 4k resolution(atleast HD).

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    1 offres

    Verilog, and neural networks expert is needed for a project

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    2 offres
    Verilog expert is needed S'est terminé left

    Verilog expert is needed for an implementation.

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    10 offres
    An LSTM implementation in Verilog. S'est terminé left

    A Verilog, and FPGA expert is needed for the price shown.

    €10 (Avg Bid)
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    3 offres
    Dịch vụ SEO SEO4SALE S'est terminé left

    Dịch vụ SEO Google uy tín tại [se connecter pour voir l'URL] - SEO4SALES Web: [se connecter pour voir l'URL] Bản đồ: [se connecter pour voir l'URL]%8Bch+v%E1%BB%A5+SEO+Outsoure+-+SEO4SALES/@10.757465,106.644593,15z/data=!4m5!3m4!1s0x0:0x5473004eb6ebf645!8m2!3d10.757465!4d106.644593 GG Folder: [se connecter pour voir l'URL] AboutMe: [se connecter pour voir l'URL] Ang...

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    4 offres
    verilog coding S'est terminé left

    Verilog coding on Xilinx FGPA

    €15 / hr (Avg Bid)
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    9 offres
    MIPS 32 architecture S'est terminé left

    I need a design a MIPS 32 based simulink model in verilog. It is very basic with few operations like add sub load and branch.

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    verilog expert needed-2 S'est terminé left

    i want long term employee. if you are expert in verilog, please bid here. Need to implement LSTM in verilog

    €99 (Avg Bid)
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    5 offres
    verilog expert needed-1 S'est terminé left

    i want long term employee. if you are expert in verilog, please bid here. Need to implement LSTM in verilog

    €3 / hr (Avg Bid)
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    1 offres
    verilog expert needed S'est terminé left

    i want long term employee. if you are expert in verilog, please bid here. Need to implement LSTM in verilog

    €3 / hr (Avg Bid)
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    2 offres
    Verilog Coder S'est terminé left

    I have a model that needs to be replicated in verilog.

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    20 offres
    Verilog programming S'est terminé left

    Need someone familiar with verilog programming in Questasim.

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    17 offres