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    2,424 e1 verilog travaux trouvés au tarif de EUR
    Systemverilog-UVM tracer S'est terminé left

    Tracer using System verilog & UVM

    €247 (Avg Bid)
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    4 offres
    verilog project mips S'est terminé left

    MIPS ALU design

    €27 / hr (Avg Bid)
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    1 offres
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    1 offres
    Arduino, FPGA expert 6 jours left
    VERIFIÉ

    I have a Arduino sketch with Motor control. I want to change this code into VHDL or Verilog HDL. This is simple project. If anyone knows Arduino and FPGA, it takes one day to do it.

    €145 (Avg Bid)
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    11 offres
    VHDL Verilog 6 jours left
    VERIFIÉ

    Kann mir jemand helfen dieses Verilog Problem zu lösen?

    €39 (Avg Bid)
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    1 offres

    Create a project about a 128x3 (128 words, with 3 bits at each word) single-port RAM in Verilog, simulate the design, and load it into the Cyclone IV chip on the DE0-Nano board. The design uses two push-buttons and one DIP switch as inputs. •One side of the DIP switch clears the memory address (not the memory contents). •The depressing of the first push-button indicates a memory write...

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    6 offres

    I need parse Verilog (vhdl) code for fpga, structure the same code and rewrite to another fpga. The project is ready.

    €3438 (Avg Bid)
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    DVLSI project 'ASIC design of face detection using haar wavelet'. Use verilog, FPGA and Viola Jones algorithm

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    3 offres

    compiling email data in excel by visiting website – link given -tripur embroidery - dt 9-10-2019 Hi i will supply website link and would want company name , email id (different email ids in different columns) , contact name, contact no. in an excel to build up mailing list website link : [se connecter pour voir l'URL] it has alphabetically organized company name and links to com...

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    41 offres

    I need someone who knows verilog. I will provide the complete details in the chat.

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    1 offres
    FSM in verilog S'est terminé left

    I have been tasked to write a FSM in verilog. The details are in the attached file. I have also attached a previous code I wrote to change ASCII into 7 segment displays, as I know that will be helpful to completing the FSM.

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    E1 Visa Help Needed S'est terminé left

    Hi, I was filling an E1 visa but there is one thing I need to fill that is DS-156E. "our employer must complete a DS-156E" I don't have an employer there. I do have a business here in my country and have an online website where I am getting orders from clients around the world but most 75% of my clients are from the US Let me know if there is anyone who can help me with this

    €12 / hr (Avg Bid)
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    4 offres
    office space and hotel S'est terminé left

    Taking an interdisciplinary approach, this project intends to reflects on the future of workplace and to consider the re-use of existing buildings and the creation of new relationships between public and private activities within an urban context. Create a mixed-use building - Primary Use: An office space accessible 24 hours a day to both the inhabitants of the building and the general public. -...

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    verilog ALU with test bench S'est terminé left

    I have to write the Verilog code(will post what i came up with below) for a 4-bit arithmetic/logic unit (ALU). The requirements are as follows: The ALU operate on inputs that are 4 bits wide. inputs aluin_a and aluin_b, a carry in named Cin and operation code named OPCODE. Inputs aluin_a, aluin_b and OPCODE are 4 bits wide. Cin is 1-bit wide. outputs will be alu_out and Cout. Output alu_out (wh...

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    3 offres

    I want someone who can teach me system verilog and perl language completely . I need someone who can guide me to grab a opportunity as a design verification engineer.

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    I need help building ASIC using bitmain chips. I will need the PSU, hashing boards, controller designed. Delivarables would be vHDL or verilog files, BOM, PCB layouts, etc. that would be required in producing the ASIC machine by giving such delivarables to PCB manufacturer.

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    Need some help adjusting a formula (P1) to work for cell E2. Right now P1 only works with E1

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    25 offres

    To detect circles by hough transformation in verilog. the board is spartan-6.

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    1 offres

    Hello Team, We are facing issue in configuration of Sangoma (E1 PRI) card in Goautodial 3.0

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    5 offres
    ModelSim, Verilog S'est terminé left

    This should include the Verilog HDL code of your MPZ design and simulation results to show the correct behavior, or any other interesting observation (e.g. maximum clock frequency of the design).

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    I've designed some verilog code, though it isn't working as expected- seemingly as I don't have enough experience with the terminology of the language. The code monitors a +12V/-12V Squarewave line. An external system drops the +12V portion of the Squarewave to 9V, then 6V, and then 3V- so that the line oscillates between 12/-12, then 9/-12, then 6/-12, then 3/-12 (all in volts). W...

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    Circuit Design Engineer S'est terminé left

    We are looking for a talented and driven hands on Electrical Engineer who will be part of creating an incredible cutting edge technology system. And will focus on the design, construction, and troubleshooting of compact and reliable embedded electrical systems . This includes electrical sub-system design, integration, PCB layout, and frequent hands-on work in lab building and debugging electrical ...

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    I need a verilog code that create a 16 bit "Calculator" that uses the slide switches as binary input, and uses the push-button cross as action triggers. The accumulator value should be displayed on the seven segment display in hexadecimal. the center button should be clear, and the four buttons should be ADD, SUBTRACT, AND and XOR.

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    Looking for excel vba expert to help write a vba macro for following logic: Steps: Setting the period (first and last column where code should be executed) 1. First column = Today's date + E1 2. Last column = Today's date + F1 Push out logic 1. Match the AZs (E8:E24) to Gap/Excess (B63:B77) 2. For each matching AZs, if there is a excess (above 0, positive value) push the value in push/...

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    Somos un call center argentino que trabaja con multicampaña. Necesitamos crear 3 VM (Maquinas virtuales) en un servidor Dell. En las 3 VM se deben instalar la versión mas reciente de Issabel (Central Telefónica). Debe esta bajo SO Linux. Parámetros: Configurar troncales y rutas salientes: Troncales: 1 Gateway synway GSM de 16 canales 1 Gateway Openvox GSM 12 canales...

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    FIR filter Design using FPGA S'est terminé left

    I require a working code in verilog/VHDL/C for an FIR Filter to be implemented on an Altera FPGA

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    ----------------------------------------------------------------------------------------------------------------------------------------- The requirements : fix neural network *To build everything in Verilog, *The accuracy test by using the MNIST database and the training function *To find out the best accuracy it can be and the time take in training. *All of this should be printed in the ...

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    FPGA DESIGN ENGINEER S'est terminé left

    We are seeking 1 FPGA Design Engineer for our new product development. FPGA Design Engineer Responsibilities: • Completing implementation in RTL • Ensuring robust and complete timing constraints • Optimizing FPGA code to balance performance, area, power, complexity and timing • Determining and executing development, integration, bring-up and test plans. • Working closely ...

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    Eye pupil tracking S'est terminé left

    I would like to do project in human eye pupil tracking system for video sequence using Verilog in Xilinx spartan 6 FPGA. Here with attached my equirements Requirements: 1. Find the pupil center coordinates and radius for various eye's. 2. Coordinates should be constant intervals while tracking. 3. Only video sequence to be used.... Not for image. Kindly send me possibility of above …...

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    2 offres

    i need a 8-bit comparator characterizing overdrive, to be implemented on FPGA, using Verilog also I need the constrains file

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    FPGA/VHDL/Verilog S'est terminé left

    Looking for implementation of a Ethernet Tester, generating and analyzing Ethernet traffic at 1G and 10G. More details on PM. J

    €11 / hr (Avg Bid)
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    25 offres
    Camera development S'est terminé left

    Opal Kelly front panel, C++, Verilog, XEM6010. Must have experience with Opal Kelly front panel, since this project will be similar with the EVB100X-DEV. Same concept, but different sensor.

    €2022 (Avg Bid)
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    build opencl code S'est terminé left

    ----------------------------------------------------------------------------------------------------------------------------------------- The requirements : Build a deep neural network using some of approximate MAC UNIT, *To build everything in Verilog, *The accuracy test by using the MNIST database and the training function *To find out the best accuracy it can be and the time take in traini...

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    10 offres

    ----------------------------------------------------------------------------------------------------------------------------------------- The requirements : Build a deep neural network using some of approximate MAC UNIT, *To build everything in Verilog, *The accuracy test by using the MNIST database and the training function *To find out the best accuracy it can be and the time take in traini...

    €156 (Avg Bid)
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    There are three data files 1. Organizers and Events Requirement Validate emails Remove records that do not have emails that validate Provide 2 files: a). File - with records that only contain validated emails b). File with old data - email not validated 2. Exporters Requirements a) Shorten Product Category Name - in all Product Category 1-7 columns Keep short name the same in all columns b) ...

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    Hi. I have a Terasic De1SoC and would like to learn how to use it. I am completely knew and have seen content from a similar project and interested on these topics About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design Implementing various encryption and decrypt algorithms SystemVerilog VMM Methodology OVM Methodology UVM Methodology I have C programming background

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    Need example code de-10 S'est terminé left

    I need a sample code on DE-10 code for utilizing the FPGA-HPS bridge with more emphasis on hardware acceleration. (C ,VHDL prefferd /Verilog). I am trying to explore the functionality where I can write some data from HPS to the FPGA. let the FPGA process it and HPS read back the result. I need to see some processing happening in FPGA on request from HPS . IT could be as simple as AND impleme...

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    Project for Marina L. S'est terminé left

    I need an "and" keyword search program, that I will describe as if it is in Excel, but it doesn't need to be an Excel program. In Excel column A, and in each cell down to a maximum of about 850,000 rows, there will be a list of words 50 to 1000 characters long. For example: A2: cat dog rabbit mouse trap... A3: table chair stool lamp ... A4: car truck motorcycle parts ... A5: comp...

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    my project is about lipstick made from natural organic materials. High Quality My website in Vietnamese, you can make it with english than i give you the translation for vietnamese version I need the website easy to SEO with all tag / onpage SEO. + Chat and call button + Link to facebook pages, likes and share button + Faecbook pixels for facebook ads intergrated to action of users + Google ana...

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    Map page will be full map with 2 layer: Origin layer (from OSM) and KML layer KML layer will be provide as in attachment User interact with map will be similar to wikimapia in which user hover over a place it will light up (see attached image) when click to a place it will show custom content with link to forum custom content is similar like this http://wikimapia.org/#lang=vi&lat=20.944607&...

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    Complete few tasks on Verilog software

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    Code on Verilog S'est terminé left

    Complete few tasks on Verilog software

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    I have a map with coordinates (attached) I need a program that allows me to easily plot the location of accidents on this map. if i have a list of accidents, (say E1, A4, J7 etc) I need to be able to enter those coordinates and see them plotted on an online version of this map - (should be shows as a Red Dot or something that is small but visible) This needs to be highly interactive User Friend...

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    HW Help w/ Verilog & Vivado S'est terminé left

    Hey looking for some help with some introductory logic building using Verilog code on the vivado software. Also Its for basys3. It’s really elementary and if you know how to use vivado this should be quick and easy money for you. Thanks

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    Compile a verilog code S'est terminé left

    I need help in compiling a verilog code. I have already built a code that runs on a platform but when i run it on multisim, it gives me errors. I need an expert to guide me with this

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    Simplistic Matrix engine S'est terminé left

    I want to create a simple CPU the do some mathematics logic between two matrices using Verilog code

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    Hi, I need to emulate a crystal oscillator circuit (attached) based on wave digital filter (WDF). Basically we aim to have WDF emulation that match a Spice simulation (e.g. in Cadence). I Already have the circuit simulated in Cadence (the output attached) . Attached, my circuit (Crystal Oscillator) schematic that needs to be mapped to WDF along with its output waveform, you will notice that there ...

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    Magento 2 issues fix S'est terminé left

    E1. Registered users are not able to use the eway payment shows as invalid card but with guest users it is working. E2. Few design changes on the front end page, 1) the Logo should be increased 2) when the product is added to the Cart through mobile, the search and cart are getting overlapped and 3) remove the address from the contact us E3. During the registration, the mobile number validati...

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