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    3,078 e1 framer vhdl travaux trouvés au tarif de EUR
    un mini formulaire S'est terminé left

    J’ai besoin d’un très petit script de page web qui formule un lien internet composer d’un préfix (SA) statique (qui ne change pas) d’une partie (E1) dynamique qui est un ‘echo ‘ d’un champs du formulaire (F1) d’une autre partie statique (SB) et d’une fin également (E2) dynamique qui est un ‘echo‘ d’un cha...

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    écrire un code vhdl , pour DE0 nano , permettant de lire la température a partir d'une entrée analogique avec un LM19 et en sortie il faut emmètre des son avec un buzzer ( différent fréquence en fonction de la température )

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    Nous avons la possibilité de produire des ASIC en quantité, nous avons une usine en chine, et nous voulons joindre la vague des miner de crypto monnaie .. Nous recherchons un passionné qui saura designer l'ASIC pour miner différente monnaie etc .. Merci

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    architecture globale projet VHDL S'est terminé left

    je suis suposé faire un projet en VHDL de A jusqu'à Z , je manipule bien le logiciel je peux decrire aussi que simuler et implémenter sur une carte FRGA , mais je me crois pas au niveau pour bien choisir un sujet ( je suis débutant , je connais pastrop sur ce que peut faire ce merveilleux logiciel ) aussi que faire l'architecture globale du projet

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    VHDL Firmware Expert needed 6 jours left
    VERIFIÉ

    I've FPGA based ADC/DAC board. Currently I'm looking for an VHDL expert using Altera(intelFPGA) tool. Please share your experience in the proposal. Which FPGA chip did you use before?

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    Hello! I need someone with experience with Framer or inVision. The task is create an interaction using 3 layers as the wireframe attached. The example is the transition between the page first to the second. If u want try with other program, let me know. The transition example will be like this [se connecter pour voir l'URL]

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    Need a A gram chicken coop for 6 chickens. Pictures available. In measurement of inches.

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    its given a full non directiona graph g=(v,e) with postive weight on their edges. create an algortih which is going to produce a in-short sub graph g1=(v,e1)(e1 contains e) in order to |e1|=|v|+3 +1 more sub question It is similar to that they are 10 problems if you can solve this one please provide me the solution and can provide you the rest

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    Digital Clock 9 heures left

    Design Digital clock in VHDL on basys 3. 24h display & hours & minutes. 1 Mhz. Preferable using Vivado.

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    Hello, we need create automated script that will started from windows then will be auto restarted and auto boot to after reboot and procee will be like this: 1, in script we will define what IMAGE will be choosen for restore whole hdd 2, under windows we will run an script what will auto reboot computer and run c*lonezilla 3, automatically will be selected all thinks --> image --> hdd 4, ...

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    Project for Loganathan N. S'est terminé left

    Hi Loganathan N., I noticed your profile and would like to offer you my project for school. A four-digit counter shall be implemented for the Basys3 FPGA development board(VHDL). We can discuss the price and I can sent the project details if you are intersted.

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    FPGA programming experts (ONLY VHDL) shall participate. This project requires establishing communication with FPGA through external current and voltage sensor. I have sensors and FPGA with me. It is required to establish the communication (both serial and parallel) using vhdl language. Interested participants can bid, I will share further information through IM.

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    Hello Freelancers I have multiple tasks in following fields of electrical engineering: • Digital Signal Processing • Digital Communication • Communication Engineering • Multimedia Communication and IoT • ASIC Design (VHDL) • Electronic Instrumentation (Multisim) • Control system (Matlab coding) • Microwave Communication systems • Microprocessors and In...

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    UI/UX Wireframing Expert S'est terminé left

    Job Description We are looking for a user-experience (UX) designer able to understand our business requirements and any technical limitations, as well as be responsible for conceiving and conducting user research, interviews and surveys, and translating them into sitemaps, user flows, customer journey maps, wireframes, mockups and prototypes. The UX designer will also be expected to design the ove...

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    Do-254 verification vhdl S'est terminé left

    Functional verification checklist

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    中国のアプリケーションである闪送(Shansong)と似たアプリ開発を行います。 デリバリーアプリ開発です。 弊社で用意しているのは 1. Framerを使ったプロトタイプ 2. プロジェクトマネージャー 3. サーバーエンジニア 4. デザイナー 弊社が必要なもの 1. ポートフォリオ 開発アプリ(A:ユーザー用、B:デリバリースタッフ用) App A: [se connecter pour voir l'URL] App B: [se connecter pour voir l'URL]

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    Project for Ahmed M. S'est terminé left

    السلام عليكم بشمهندس احمد ممكن اطلب من حضرتك بعض النصايح في الي تخليني اشتغل في مشاريع embedded systems , VHDL انا طالب بكلية الهندسة قسم كهربا وكنت عايزك تعرفني اتعلم ايه وابدأ ازاي

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    I need a vhdl code S'est terminé left

    My project is 6 bit pipeline adder with 3 different cases I need to write the code and simulate the output by tommorow night ( both vhdl and test bench)

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    generated neural network in matlab from data using nntool Using Simulink to Deploy a MATLAB Algorithm on an FPGA using systeme génerated in xiling to géneration vhdl code

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    Project for Farzeen K. S'est terminé left

    We need thesis writers proficient in VERILOG , VHDL and MATLAB to write a thesis which include coding and documentation

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    Create a thesis S'est terminé left

    We need thesis writers proficient in VERILOG , VHDL and MATLAB to create a thesis which include coding and documentation.

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    7 offres

    Statemachine generation

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    Computer Architecture -- 2 S'est terminé left

    Hello I need help with VHDL code

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    Computer Architecture S'est terminé left

    Hello, I need help with VHDL code using Xilinx Vivado.

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    hello,, I want a website that show the name of a company with a number (e1). that number indicates the number of updates that company url has. These urls uploads something called "Security Updates" its updated at lease once a month, but some of them has multiple updates a day. For example, red hat has 1 update today, and 9 updates yesterday: [se connecter pour voir l'URL] *Based o...

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    FPGA PROJECT —2 S'est terminé left

    A “garage” door opens and closes with vhdl language for basys 3 and nexys 4 and design multisim

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    FPGA PROJECT -- 2 S'est terminé left

    A “garage” door opens and closes with vhdl language for basys 3 and nexyx 4 and design multisim

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    FPGA PROJECT S'est terminé left

    A digital clock with 1 Mz 6 display on Basys 3 amd nexys 4 with alarm in VHDL

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    Optimization Expert using XGBoost S'est terminé left

    I have predictive python code, but I have to build Optimization code. I want to have the optimization part finish as well, after that I will send the results for evaluation for the optimization part there are three parts, you need to calculate L= E * I**2 /1000 E is energy I is index which is the output that we already calculated in prediction ( 809 results of test set) and need to maximize L E ...

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    Project Details Dear all I have board Xilinx Spartan-3A. My project divided into two parts:- 1. The first part is interfacing ADC with FPGA Spartan- 3A I have two external sinusoidal signals with different frequencies. One of these signals is (50Hz) and the other is ( 30KHz). These two signals I want to be entered to Spartan-3A kit through ADC (J22 ) through channel VnA and VinB for the kit i...

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    Project Details Dear all I have board Xilinx Spartan-3A. My project divided into two parts:- 1. The first part is interfacing ADC with FPGA Spartan- 3A I have two external sinusoidal signals with different frequencies. One of these signals is (50Hz) and the other is ( 30KHz). These two signals I want to be entered to Spartan-3A kit through ADC (J22 ) through channel VnA and VinB for the kit i...

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    We require these files to be printed to PDF, and exported as DXF and DWG format. [se connecter pour voir l'URL] [se connecter pour voir l'URL] [se connecter pour voir l'URL] [se connecter pour voir l'URL] 678wM&[se connecter pour voir l'URL] 678wM&[se connecter pour voir l'URL] 678wM&[se connecter pour voir l'URL] [se connecter pour voir l'URL] ...

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    create a VHDL code S'est terminé left

    this project is a VHDL code and microprocessors. more details in the attached file.

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    fpga implementation of ofdm-im S'est terminé left

    only simulation using labview or verilog / vhdl or simulink

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    vhdl related problems S'est terminé left

    Vhdl problems for educational purpose, inbox me for further understanding

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    10 offres

    Vhdl project, deadline is next 20 hours

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    I need a VHDL expert to work for me S'est terminé left

    The project is to design a digital system in VHDLusing Vivado. The board is Basys3.

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    Embedded system and VHDL Researches S'est terminé left

    I'm looking for computer engineer or any one who can help me to did a research about the two topics as follows 1) Hardware Description Languages Details : Write a research article on the state-of-the-art of hardware description languages. The length of the article must be 3000 words at least 2) Embedded Systems Details: Write a research article on the state-of-the-art of embedded systems....

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    Page 1 * Create a landing page * Users must be able to sign up with their Email, Phone, Username, Full Name, and Age * Email confirmation must be sent * Phone number must be verifiable * Via Text and 4 Digit Code Page 2-6 * Users will be redirected to a questionnaire with 5 questions (1 question per page) * Example Questions: * Select which fits your profile (Can not be skipped...

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    The requirement is Iets say we have an excel in which there are two sheets(Sheet1 & Sheet2) In Sheet1 I have four cells(A1,B1,E1,F1) which gets updated every minute by pulling the data from the web. C1 value= B1-A1 and G1=F1-E1. D1 remains blank Now I need help in designing Sheet2 with below requirements [se connecter pour voir l'URL] A1 data should be pasted to Sheet2 B1 after 1minute ...

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    VHDL Expert needed -- 2 S'est terminé left

    VHDL Expert needed with good knowledge of state machines

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    VHDL Expert needed S'est terminé left

    VHDL Expert needed with expertise in designing state machines and coding them

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    VHDL traffic controller -- 2 S'est terminé left

    I need someone to do who has experience in VHDL. Need someone to do a VHDL coding for me.

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    I need a VHDL Designer S'est terminé left

    I don't have time to do my Vhdl project due to having been sick. The project is a crude design of how a vending machine is supposed to work. Entities are provided but architecture is to be done. I don't need all the points only half should suffice. To be done by sunday 4:00. It shouldn't be too complicated.

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    we have a postgresql. we have a script to create mailboxes in the postgresql. we want the mailboxes created on the postgresql to receive messages. only receive. we are also adding redirects. redirection example: send@[se connecter pour voir l'URL] redirects to send@[se connecter pour voir l'URL] to finish we also add mailbox redirection to mailboxes external to the server. We alread...

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    Need Javascript developer S'est terminé left

    Various JavaScript programs requested Here are the problems that must be solved to complete this job and receive payment. I welcome your quotes. Thank you. E1) Write a function called productOfValues which takes in an object of key/value pairs and multiplies the values together. You can assume that all keys are strings and all values are integers. E2) Given an array of users, write a function,...

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    FPGA VHDL RTC MCP7940N on I2C S'est terminé left

    I want to have a RTC MCP7940N code written in VHDL in Vivado by xilinx fo Artix-7. There need to be a TestBench to see how it works. I want to use it to see logs in simple notepad with time hh:mm:ss . This is what I already made. That is only module.

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    Frame builder S'est terminé left

    Hello , i have an VHDL project it is a frame builder (Quartus II)

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    Extended kalman filter S'est terminé left

    Need to design an extended kalman filter in vhdl

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    Based on requirements write testcase - input and expected output Top level testbench Simulation Document the procedure

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