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    2,510 e1 framer verilog travaux trouvés au tarif de EUR
    Systemverilog-UVM tracer S'est terminé left

    Tracer using System verilog & UVM

    €248 (Avg Bid)
    €248 Offre moyenne
    4 offres
    verilog project mips S'est terminé left

    MIPS ALU design

    €27 / hr (Avg Bid)
    €27 / hr Offre moyenne
    1 offres
    Build a CNN 5 jours left

    Hi, I need : * CNN IN FPGA using my mac unit? *Verilog *MNIST DB

    €189 (Avg Bid)
    €189 Offre moyenne
    6 offres

    Need basement framed. Labor only — no materials needed. Should only take a day.

    €349 (Avg Bid)
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    4 offres
    Basement framer 9 heures left

    Need basement framed. Labor only — no materials needed.

    €300 (Avg Bid)
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    3 offres

    I need a sample code on DE-10 code for utilizing the FPGA-HPS bridge with more emphasis on hardware acceleration. (C ,VHDL prefferd /Verilog). I am trying to explore the functionality where I can write some data from HPS to the FPGA. let the FPGA process it and HPS read back the result. I need to see some processing happening in FPGA on request from HPS . IT could be as simple as AND impleme...

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    I need an "and" keyword search program, that I will describe as if it is in Excel, but it doesn't need to be an Excel program. In Excel column A, and in each cell down to a maximum of about 850,000 rows, there will be a list of words 50 to 1000 characters long. For example: A2: cat dog rabbit mouse trap... A3: table chair stool lamp ... A4: car truck motorcycle parts ... A5: comp...

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    Your challenge: Deploy a working app to apple store in 10 days. By 8/17/19. If you do well, you will be given ALOT more opportunities and work. The app will have 6 pages and is very similar ot an e-commerce type of flow: 1. Email sign up 2. Ask a question 3. Show a special product (the most popular.. just 1 product) 4. Show product details. 5. Buy the product 6. Show a list of additional prod...

    €1148 (Avg Bid)
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    my project is about lipstick made from natural organic materials. High Quality My website in Vietnamese, you can make it with english than i give you the translation for vietnamese version I need the website easy to SEO with all tag / onpage SEO. + Chat and call button + Link to facebook pages, likes and share button + Faecbook pixels for facebook ads intergrated to action of users + Google ana...

    €370 (Avg Bid)
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    Map page will be full map with 2 layer: Origin layer (from OSM) and KML layer KML layer will be provide as in attachment User interact with map will be similar to wikimapia in which user hover over a place it will light up (see attached image) when click to a place it will show custom content with link to forum custom content is similar like this http://wikimapia.org/#lang=vi&lat=20.944607&...

    €174 (Avg Bid)
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    Complete few tasks on Verilog software

    €75 (Avg Bid)
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    12 offres
    Code on Verilog S'est terminé left

    Complete few tasks on Verilog software

    €59 (Avg Bid)
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    7 offres

    I have a map with coordinates (attached) I need a program that allows me to easily plot the location of accidents on this map. if i have a list of accidents, (say E1, A4, J7 etc) I need to be able to enter those coordinates and see them plotted on an online version of this map - (should be shows as a Red Dot or something that is small but visible) This needs to be highly interactive User Friend...

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    HW Help w/ Verilog & Vivado S'est terminé left

    Hey looking for some help with some introductory logic building using Verilog code on the vivado software. Also Its for basys3. It’s really elementary and if you know how to use vivado this should be quick and easy money for you. Thanks

    €21 (Avg Bid)
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    Compile a verilog code S'est terminé left

    I need help in compiling a verilog code. I have already built a code that runs on a platform but when i run it on multisim, it gives me errors. I need an expert to guide me with this

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    Project for Chris H. S'est terminé left

    Hi Chris, I looked over your profile and believe you may be the perfect fit for one or multiple projects we have. We currently have a chat translation app that is written natively for iOS and Android, and also works in the browser. We would like to utilize the same backend API, which uses sockets and uses Nodejs. I also believe the database is using mysql, but I'm not entirely sure. This is s...

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    Simplistic Matrix engine S'est terminé left

    I want to create a simple CPU the do some mathematics logic between two matrices using Verilog code

    €255 (Avg Bid)
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    Hi, I need to emulate a crystal oscillator circuit (attached) based on wave digital filter (WDF). Basically we aim to have WDF emulation that match a Spice simulation (e.g. in Cadence). I Already have the circuit simulated in Cadence (the output attached) . Attached, my circuit (Crystal Oscillator) schematic that needs to be mapped to WDF along with its output waveform, you will notice that there ...

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    Looking for designer S'est terminé left

    I am looking for designer to finish my logos and promotional images. He or She must have 3 years of experiences in design. Must be familiar with Adobe Photoshop, InVision, Principle, Framer ... Design sketches will be given in direct messages.

    €468 (Avg Bid)
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    Magento 2 issues fix S'est terminé left

    E1. Registered users are not able to use the eway payment shows as invalid card but with guest users it is working. E2. Few design changes on the front end page, 1) the Logo should be increased 2) when the product is added to the Cart through mobile, the search and cart are getting overlapped and 3) remove the address from the contact us E3. During the registration, the mobile number validati...

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    I have a task on verilog and i want someone who is experience on it to help me with it. Please bid only if you know youre an expert. I will share details with interested freelancer. Budget is limited, hiring will be on a weekly basis

    €22 (Avg Bid)
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    3 offres

    Hi, I need a basic example of a state machine in VERILOG. We need to find the pattern "100" using machine states. We have 4 states: S0: Initial state S1: If 1 is found S2: If 0 is found S3: If 0 is found Encoding: S0: 00 S1: 01 S2: 11 S3: 10 Transition: Actual state / Input / Next state 00 - 0 - 00 00 - 1 - 01 01 - 0 - 11 01 - 1 - 01 11 - 0 - 10 11 - 1 - 01 10 - 0 - 00 10 - 1 - 01 T...

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    I posted this a couple weeks ago but decided that the process was not in the direction I want to go for the future. I deleted the original post and welcome those that placed a bid to do it again. I am replacing my current E1 system that was developed to manage psychic calls, due to changes to the Telecommunications industry in Australia and am moving towards SIP service providers to meet my need...

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    Wanted Online FPGA Tutor S'est terminé left

    To Teach : About VLSI Advanced Digital System Design VHDL Verilog RTL Design FPGA Design SystemVerilog VMM Methodology OVM Methodology UVM Methodology

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    Existing Issues / Fixes Required: E1. During the registration, the mobile number validation should only be 04XXXXXXXX but not rest of the letters (048XXXXXXX consider as invalid phone number but it is actually valid phone number) E2. When customer selects the product and click on Cart, there is a Sign in option that displays on top side and it is observed that – the sign in from there is n...

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    FPGA Development S'est terminé left

    More than 2 years of experience in FPGA design and development area. Candidate should have working Industry experience in below skill set:- •Working experience to process received frequency chirplet data using FPGA and to transmit processed data by interfacing FPGA with Radio Frequency (RF) transceiver module ADRV9009 and 10 Gigabit Ethernet Media Access Controller (10GEMAC). •Working ...

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    Embedded systems designers S'est terminé left

    Needs to hire 3 Freelancers We are a small and growing company offering consulting and engineering services in many different areas of industry. Here you can find more about us: [se connecter pour voir l'URL] In order to enforce our team, we are seeking embedded systems designers with experience in the following domains: * PCB design (Altium Designer, Eagle, KiCAD, PCAD...) * Firmware design...

    €501 (Avg Bid)
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    Build a neural network S'est terminé left

    Hi, I need : * ANN IN FPGA using my mac unit? *zybo-zynq-7000-arm-fpga-soc-trainer-board/ *verilog *MNIST

    €16 (Avg Bid)
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    2 offres
    8 bit processor S'est terminé left

    fix bug in verilog hdl for 8 bit

    €23 (Avg Bid)
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    Design an 8-bit microprocessor using Verilog HDL by using Structural Verilog modelling. The individual components can be designed using behavioral modelling. Mandatory components: Instruction Memory Register File Data Memory ALU Control Unit Multiplexers Sign extend unit Program counter The Register File has two registers R0 and R1. Design the program counter and instruction memory such that input...

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    Enable all the listed hardware as the attached image. (2xMarvell ETH, MIG-DDR3, SD, QSPI Flash, PS-DDR3, uart) 2. Install Configured Petalinux, with Python, Flask, numpy, Pillow, littleCMS . Boot with QSPI (We will access this board on the Ethernet, make ETH0 DCHP and ETH1 Fixed @ [se connecter pour voir l'URL]) 3. Display JPEG/TIFF image file from SD in webpage. 4. Add one function ...

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    I have the algorithm of what I want to implement, I just need help a second eye to help me understand how to implement it.

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    6 offres
    RS-FEC 198,194 verilog code S'est terminé left

    VLSI design for Reed Solomon FEC for 198,194 including documentation and explanation. Verilog files and simple testbench to prove the design. ASIC

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    I am looking for someone who can design a FPGA based hash algorithm including blake bmw sha512 skein luffa shavite simd echo hamsi shabal whirlpool and jh. Developer need to complete FPGA bitstream, and provide verilog source codes.

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    This project needs an expert in Office 365, Azure, and O365 Security Configuration. Please do not bid unless you have read the below requirements and you understand them. Payment will be made in Canadian Dollars. Project Completion Due Date: Under 30 days from award date. Please see milestone deadlines below. Basic Description: this is a quick turn around project that needs to be completed ASA...

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    Build me verilog project S'est terminé left

    I want to implement a paper using verilog coding.. Kindly review paper before biding

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    *FAILURE TO ANSWER MY QUESTIONS BELOW WILL RESULT IN IMMEDIATE DELETION OF YOU QUOTE* Hello artists, I'm looking for an illustrator potentially create ten comic book issues. Each issue will be 22 pages long and full color. The theme is fantasy (magic, swords, and shields) and will include some very dark erotic scenes as well as graphic violence, graphic sex, and foul language. Please do not...

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    Pipelined dual thread core processor design using system verilog, quartus software and altera development board. Please read pdf for detailed information.

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    5 offres
    Verilog Expert S'est terminé left

    Anyone who has hands on in verilog on An Accelerator-Based Video Display can help me

    €222 (Avg Bid)
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    3 offres
    Project on verilog S'est terminé left

    Anyone who is good in verilog and worked on Accelerator-Based Video Display can ping me

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    3 offres
    Verilog task S'est terminé left

    Anyone who has experience or worked on An Accelerator-Based Video Display using verilog can consult me.

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    HDMI using cyclone V S'est terminé left

    Display image on the monitor using cyclone V fpga (tool quartus prime Lite edition) , i2c controller using qsys must be used to connect to hardware using verilog.

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    Hello, Server has Centos with Asterisk and Freepbx Need help, to setup pbx server and Sangoma E1 card thanks in advance! Regards, CP

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    Technology research is already done. Internal FPGA system architecture is already designed. Therefore we only need you to implement and document it. Project is already split and documented as 10 milestones so that development can be done incrementally, step by step, and reviewed/monitored. Project is mostly Verilog development. Some simple programming necessary as well. Documentation is required...

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    We need a Verilog/VHDL developer to write some simple blocks for the Virtex-7 FPGA. The development environment is Xilinx Vivado. There are 5 blocks in total with the following functionalities: 1. CM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and testbench. 2. RDM Memory: Write a wrapper for the Xilinx xpm_memory to fit our bus requirements and test...

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    In this project, you are required to develop a structural Floating-Point Unit (FPU) for use with a microprocessor. The processor needs to be capable of floating point addition and multiplication. The numbers are to be encoded into IEEE 754 single precision 32-bit format. The FPU should also be able to detect and flag the 'NaN' cases. For the project demonstration, interface the FPU to...

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    FPGA Content Writer S'est terminé left

    We are looking for an experienced FPGA developer to write technical documentation related to Xilinx and Verilog development as well as custom hardware accelerators. Content is in the form of educational papers for semi-technical audience. Each article/paper is expected to be around 1900 words (4-5 pages, plus custom diagrams/infographics). Candidates must be able to prove experience in RTL/Verilo...

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    Hello, Need to setup Asterisk server, with Sangoma PCI Card for asterisk voip server Carrier Siptrunk TDM with Audio Codec E1-PRI Best regards, CP

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    I have 2 schemes. One with neuron and with genetic algorithm. I need to combine both to train this neuron via genetic algo. Using VHDL in ISE design suite 14.7. Here is [se connecter pour voir l'URL] picture of two symbols that I want to combine(gen - genetic algorithm with build in neuron process, neur4sigm - neuron with sigmoid func). I need to train this neuron with this alforithm. You can...

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